Hi all,
When using 7343.Visio-10_ADC12J4000_4000MSPS_1FPGA_v2.pdf solution for realizing 4GSPS,
how do you synchronize output clock of both TRF3765?
My customer plans to use two units of TRF3765 as 4GHz sampling clock for 8 ADCs.
Whenever it switches on a power supply, it is anxious about timing, such as a rising edge of each output waveform, becoming random.
Regards,
Toshi
