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ADS1282

Other Parts Discussed in Thread: ADS1282

I have a question concerning ADS1282 data output.  The 1st paragraph of the data sheet, page 27, says:   "When reading data by the continuous mode, the data must be read within four CLK periods before DRDY goes low again or the data are overwritten with new conversion data."  According to the data sheet, pg. 5, the max SCLK period is 16/fclk  which would imply not completing clocking out the data for at least 125us (16/4.096MHz*32bits).  So I'm wondering if it's true that the data must start to be clocked out within 4 system CLK's?   Other ADC's I've used allow more time to read the data so that several ADC's can be multiplexed by enabling each ADC clock in turn and clocking out the data without having to buffer the data externally.  If I ran SCLK at its max of 2.048MHz (fclk/2), I could clock out data from 4 ADC's in 63us.  Would that work?

  • I will update this if I'm wrong, but I think the confusion is in the wording of this section.

    In the ADS1282, the DRDYn indicates that a new conversion data is coming and that the data on the register will be updated as DRDYn returns low.

    You can start collecting data as DRDYn goes low. However, if you have not completed clocking out the data before DRDYn goes high, then you must finish before DRDYn goes low again (which is 4/fclk) or the data will be updated with a new data (corrupting the read).

    Again you should be able to start reading the data as soon as DRDYn goes low and you have as long as 1/(data rate) to complete the read. Even at the fastest data rate, you should have plenty of time to clock out data.

    Joseph Wu