Hi,
We have designed an interface card with a DAC5675a for RF pulse shaping. The IO card is an FMC card that connects to a Xilinx Spartan 6 FPGA board. I have all of the data bus driven from the FPGA with LVDS25 signals. I also use this (LVDS25) interface to drive the DAC5675A clock input. I am not getting any output from the DAC. Previously I used the DAC5675A eval board interfaced to the SPARTAN6 ande the clock was single ended and that worked. I suspect the levels are wrong for the LVDS25 to the clock input. Is there a way to drive the DAC5675A clock input differentially form the LX16 Spartan 6 FPGA? It looks like I would need to add a resistive divider to drop the lvel down to +2.0V the differential swing of the LVDS is 0.5V so this meets the min differential requirement for the DAC5675A. the board is already laid out, so if I could just change differential types that would be great.