This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ads1672 sclk free running

Other Parts Discussed in Thread: ADS1672

I am interfacing the ADS1672 to a processor with the processor as SPI master.  My particular processor does not support gating the SCLK signal.  In figure 2 of the ADS1672 data sheet, SCLK is shown as idle before the DRDY pulse.  Before DRDY is generated, is SCLK ignored?  If my SCLK is free runnning, will the ADS1672 always put the MSB on DOUT on the first rising edge of SCLK after the DRDY rising edge?  Is there any timing requirement between the rising edge of DOUT and the rising edge of the first SCLK edge?  My application only has one ADS1672 attached to the processor, so I plan to tie CS low.


Thanks,

Tobyn

  • Hi Tobyn -

    If you tie CS low, you cannot have a free running close if you plan to have any idle activity by the device or the bus.  So when CS is low, SCLK is always recognized and not ignored.  You can reference the Chip Select section on page 22 of the datasheet for behaviors of the different pins.

    You could use a free running clock if you have an active CS.  The SCLK would then be ignored when CS is high.