I am interfacing the ADS1672 to a processor with the processor as SPI master. My particular processor does not support gating the SCLK signal. In figure 2 of the ADS1672 data sheet, SCLK is shown as idle before the DRDY pulse. Before DRDY is generated, is SCLK ignored? If my SCLK is free runnning, will the ADS1672 always put the MSB on DOUT on the first rising edge of SCLK after the DRDY rising edge? Is there any timing requirement between the rising edge of DOUT and the rising edge of the first SCLK edge? My application only has one ADS1672 attached to the processor, so I plan to tie CS low.
Thanks,
Tobyn