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ADS7229 with external clock

imed mabrouk
Prodigy 40 points
Other Parts Discussed in Thread: ADS7229


Hi,
I have a question about behaviour of the ADC device ADS7229.

I want to control the device in manual trigger, read while converting, EOC/Int active low mode with EXTERNAL CLOCK.
For our case, the Internal clock should not be used.

The operation sequence that we want to implement is like the one explained in page 12 (figure 2) except for the use of internal clock.

If we want to do that with external SCLK, we need to provide the SCLK during the conversion time but what about the sampling time?

Should the external SCLK be generated during tSAMPLE?

The data sheet does not give an example with external clock use so I proposed this sequence:

I added 6 SCLKs after conversion time for sampling however I think they should be added before the Nth pulse of CONVST_N. ( because for me the correct sequence is sampling then convst_n pulse ( for conversion) then after the next convst_n data can be read)

What do you think? 

Any suggestion?

Thank you.

  • 0
    TI__Expert 5705 points

    Hi Imed,

    The timing diagram you're proposing (including the placement of the 6 SCLKs for sampling) is consistent with the datasheet and looks reasonable to me. 

    Best Regards,
    Harsha

  • 0 in reply to Harsha Munikoti
    Prodigy 40 points

    Hi Harsha,

    Thank you for your reply but I have to add some additional information related to the application.

    The ADC controller (FPGA), must acquire the ADC each 50 ms.

    It follows that diagram for each acquisition (2 convst_n pulses Nth and Nth+1)

    This ADC allows us to read correct data at Nth+1 part.

    Thus data must be sampled before the Nth convst_n pulse (it is then converted during Nth reading)

    Data read at this time (Nth) is invalid (as it is 50 ms old if we follow the timing diagram)

    Correct (current) data is the one read at (Nth +1) but we have to change the timing diagram in order to sample data before Nth convst_n pulse.

    That's why I think those 6 SCLKs must be placed before the first (the Nth) convst_n pulse.

    I hope you understand what I am trying to explain. I tried to be as clear as possible.

    What do you think ?

     

  • 0 in reply to imed mabrouk
    TI__Expert 5705 points

    Hi Imed,

    I do understand your explanation. Your diagram is derived directly from Figure 2 which assumes that the starting point of the ADC conversion cycle is the falling edge of EOC (signifies "start of conversion"). Assuming the start point is the same in your diagram, the placement of the 6 sampling clock cycles as shown on your timing diagram is correct.

    Now, you can assume a different start point to the ADC conversion cycle. Figure 1, for example, assumes the rising edge of EOC (signifies "start of sampling") as the start point of the ADC conversion cycle. This is exactly what you are also proposing, except you would just read data (from the previous cycle) during the conversion phase. So I think what you're trying to do is aligned with the datasheet and should work correctly.

    Best Regards,
    Harsha

  • 0 in reply to Harsha Munikoti
    Prodigy 40 points

    Hi Harsha,

    Ok, I understand that but we don't want to use "read while sampling" sequence (figure 1) for the following reason.

    For safety reason, we want to check if the device is responding that's why we need a quick reaction from the device after setting low convst_n. This is only possible if we use read while converting mode (figure 2) because we have that falling edge of EOC immediately after convst_n falline edge.

    So In order to keep read while converting mode and to be sure that data read during Nth+1 conversion (convst_n pulse) is correct (up to date) we need to add 6 SCLKs before the Nth conversion as described in the next diagram:

    Is that still compliant with the device specifications?

    Do we need to assert CS_N low during these 6 SCLKs ?

    PS.

    The start point for the FPGA when it's commanded to acquire the ADC is a falling edge on convst_n as it's implemented today or a 6 SCLKs for sampling as I am proposing now.

    I am doing this because I think data that we are reading at the second convst_n is 50 ms old.

    Thanks again.

  • 0 in reply to imed mabrouk
    Prodigy 40 points

    Hi,

    Please I still need to check one last point with you:

    Do we need to assert CS_N low whenever SCLKs is needed even if not reading data  ?

    For example during conversion/sampling time?

    sampling time = the added 6 SCLKs

    Thank you