ads1672 sclk vs. sample clock

Tobyn VanVeghten

Other Parts Discussed in Thread: ADS1672

I plan to use the ADS1672 in an application with multiple sample rates, so the main clock on the ADS1672 will vary from 15 MHz to 2.5 MHz. If I use an external SCLK for the SPI interface, are there any issues if SCLK is faster than the main ADC clock? For simplicity, I'm planning to operate my SPI bus at the rate for my fastest sample rate for all ADC sample rates. As long as my SCLK and other SPI parameters are within the parameters listed in the table after Figure 2 in the data sheet, regardless of what the main ADC clock rate is, will this be ok? Are there any issues I'm not considering?

Thanks,

Tobyn

over 10 years ago

0 Greg Hupp over 10 years ago

TI__Mastermind 23235 points

Hi Tobyn -

As long a you meet the specs shown in the datasheet Figure 2, you should be OK with the proposed operation of the SCLK faster than the main clock CLK of the device.

0 Seishin over 10 years ago in reply to Greg Hupp

Genius 4135 points

Hello,

Is there a maximum limit of CLK / SCLK period when I want to control with a slow external SCLK?

Best regards,
Seishin

0 Greg Hupp over 10 years ago in reply to Seishin

TI__Mastermind 23235 points

Hi Seishin -
As long as you can SCLK can transmit/receive the data within the timing of a frame and you are meeting the timing specs, there shouldn't be any required ratios of the CLK/SCLK.

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ads1672 sclk vs. sample clock