600 Ms dual channel DAC

Federico:

The DAC3482 supports a max input data rate of 625 MSPS.  The device can be configured to run in word-wide format such that you get one sample out of each converter per clock pulse.  (Note, this is equivalent to operating the DAC34H84 while only using one 16-bit bus). The DAC3482 is the highest input data rate, non-JESD, dual DAC device.

--RJH

Hello,

an input data rate of 625 MSPS for both channels on a sigle input databus, means that the input data rate is doubled (DDR) and the timing requirement (for each channel) are the same of 1250 MSPS.

An DAC input data rate of 1250 MSPS DDR is really too much for the FPGA that will generate data (even for higher speed devices), in particular with a cable connection between FPGA board and the AD/DA one, as in our case.

What I really want to know, is if there is a way to use DAC34H84  each input bus for one single output (leaving 2 outputs not used) , obtaining so really an input data rate of 625 MSPS (may be in this way loosing the upsampling capability).

The alternative is to use separated single channel DAC for each channel, but TI don't seem to have the right device (we need current output to gnd, to allow I/Q DC connection with the RF modulator).

Best regards,

Federico

Yes, I know what is the DDR format, but the problem is not the clock: it is the data timing.

Suppose you have a single input channel at 650 MSPS, the timings will be like:

- bit duration: 1.6 nS

- rise/fall 0.25 nS

- probable setup/hold: 0.3 nS --> margin= +/- 0.37 nS respect to data centre

at 625MSPS DDR (or 1250MSPS, it is exactly the same), the timings will be like:

- bit duration: 0.8 nS (each channel)

- rise/fall 0.25 nS

- setup+hold (taken from DAC3482 datasheet, pag 14): 0.5 nS --> margin= +/- 0.025 nS ! practically no margin !

and note, the value used for rise/fall are not pessimistic, and are not taken into acount clock jitter or clock duty cycle !

Add trace and cable length mismatch and FPGA outputs skew, so a 625MSPS DDR input data rate is practically impossible to achieve!

This why I am searcing for an alternative solution.

Regards,

Federico

Federico:

Agreed.  The FPGA data bus speed is operating at 1250 MSPS.  Your calculations are correct and there is 50 ps of margin.  This is essentially how the max data rate is defined (i.e. the speed at which there is next to no margin with the set-up and hold times).

In a practical sense this 50 ps of margin should be sufficient.  We are utilizing FPGA based pattern generation tool in the TSW1400 to push data at these speeds without issue.  There is also a clock delay feature on the DAC to help hone in timing issues due to the impairments you mentioned.

If you really wanted to operate at a lower data bus speed then you can use the DAC34H84.  This device has a 32-bit wide bus.  You would need to send duplicate data for A and B channels and similarly for C and D channels.  This would effectively operate at a data bus speed of 625 MSPS and improve the margin.  Output channels would then be on Channels A and C.  The unused channels of B and D can be disabled.

--RJH

Hello,

using the dac34h84 in this way and centering timing for channels A and C only, channels B and D will capture wrong data: may this cause any noise problem ?

The datasheet states that channels B and D of dac34h84 can be put in sleep mode (config26), but (I suppose) the digital input section will be always active.

Best regards,

Federico