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ADC12D1800 Sample clocking delay availability in DES mode

Rajesh
Expert 1010 points
Other Parts Discussed in Thread: ADC12D1800

Hi,
As per my application I have an 12 bit ADC(ADC12D1800) for the RF signal digitalization in the range of 0.5GHz to 9GHz , In order to down convert  this in the front end of ADC I have track & hold amplifier. Both T/HA & ADC requires the sampling clock , I planned to provide 3.1GHz sampling clock to THA & 1.55GHz sampling clock to ADC(ADC will be operated in the DES mode). As per the above configuration I want 90 shift between 3.1GHz sampling clock & 1.55GHz clock.I planned to use LMX2581 as a clocking source for ADC as well as TH/A which has two o/p channels. As per my application requirement I want 90degree phase shift between 3.1GHz clock as well as 1.55GHz clock for this I planned to use delay block which is available inside the ADC. I have one query on this ADC12D1800 what is the maximum possible delay we can introduce on the sampling  clock on DES mode of operation. Whether the above circuit will work ?

Regards,

Rajesh

  • 0
    TI__Genius 13335 points

    Hello Rajesh,

    The ADC12D1800 has a coarse aperture delay adjust with 825ps of range and fine aperture adjust with 2.3ps of range and ~36fs steps.

    If I understand correctly, it sounds like you are trying to use the following configuration:

    You could use the coarse delay inside the ADC to shift by 90 degrees (~80ps) for falling center aligned data or 270 degrees (~240ps) for rising center aligned, both of which are within the range of the ADC. A 90 degree phase shift is shown below.

    Using both the coarse and fine delays of the ADC12D1800, this configuration would work. The only caution I would advise is the aperture delay adjust is limited to input clock frequencies <1600MHz. So for this application of 1.55GHz it is ok, but if you tried to exceed the 1600MHz limit you would run into problems.

    We would also recommend to use the DESIQ mode which has a little more bandwidth (1.75GHz) than DESI or DESQ modes (1.25GHz). 

    --edited

  • 0 in reply to Luke LaPointe
    Expert 1010 points

    HI Luke,


    Thanks for the reply, Yes The above images are correct both are matching as per my requirement. But I need some clarifications on the above waveform:

    I want ADC clock to be lagged by 90degree  from the TH/A clock, the above waveform shows that ADC clock leads the TH/A(hmc661lc4b) clock by 90 degree. As per my application I wants to sample the TH/A o/p at the following edge of TH/A clock & both the edges of ADC clock using DES mode of operation.


    As per my application My operating frequency will not cross beyond 1.6GHz.

    As per your recommendation I am not getting the difference between DESIQ mode , DESI & DESQ modes ?
    As per my understanding IF selected DES mode of operation by default DESI will be selected & this input will be muxed with Q channel also vice versa correct me if I am wrong ?

    Regards,

    Rajesh

  • 0 in reply to Rajesh
    TI__Genius 13335 points

    Hello Rajesh,

    Sorry for confusing you. The aperture delay does cause the ADC sampling clock to lag the T&H clock, not lead. The timing diagram would look like the following where delaying by 90 degrees (~80ps) will result in falling center aligned data.

    For the second question, the main difference between the DESI/DESQ and DESIQ modes are how the input is internally routed. Please see the following thread where I recently described the difference: http://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/t/386872

  • 0 in reply to Luke LaPointe
    Expert 1010 points
    Hi,

    Thanks for the recommendation, I already launched my PCB for the fabrication with the DESI mode. Any way I will consider this method in my upcoming designs.

    Regards,
    Rajesh