We are having some trouble using DAC3484. The problem is explained below.
The input to the DAC3484 is IQ interleaved data from for AB and CD channels (DAC3484 operates in BYTE WIDE MODE). Thus, upper 8 bits i.e. D[15:8] are being used for AB Channel and lower 8-bits i.e. D[7:0] are being used for CD channel. The data transfer is as per recommended datasheet of DAC3484 shown below for byte-wide mode data transfer.
Now, if we want to transmit a single sine tone from DDS compiler inside FPGA which is tuned to 10 MHz will generate I and Q components, which then interleaved in above described format and transmitted to DAC on rising and falling edge of DATACLKP/N(DDR). The signal goes to both the channels i.e to both Channels AB and CD for interpolation, mixing and to analog conversion via inverse sinc filters.
Suppose, if DAC mixer is bypassed, the output from both channels is OK from both DAC channels A and C (DAC Channels B and D are not used). This has been checked more than 100 times by re-fusing bitfiles.
But, when DAC mixer is enabled ( whether NCO or Fs/8 Mixer is used to up convert or modulate the incoming signal by fixed 80 MHz {Fs/8= 640M/8= 80 MHz}), the output from the DAC channels both A & C, got corrupted. If a 10 MHz signal is given to DAC when modulated by 80 MHz, gives output at 90 MHz. Getting a single tone at 90 MHz is a good case (DAC behaviour is OK) but when output is corrupted, DAC output shows two tone i.e. at 70 MHz and 90 MHz.
The signal amplitude levels of both 70 MHz and 90 MHz components are not same (seen in Spectrum Analyzer, difference in gain is 12 dB). The probability of getting corrupted output in Channel A (1 out of 30 times is corrupt approx…) is lesser than Channel C (4 out of 10 times is corrupt approx.. ) and the probability changes board to board. This has been checked by re-fusing the same bitfile on board.
It appears that DATA SIGNALS I and Q of each channel get one sample delay in either I-Q arm which cause phase imbalancing and produces corrupted output.
Concluding, the problem is in the synchronization of DAC input signal such that it correctly modulates the input signal with 80 MHz component.
The input data sampling rate : 160 MSPS
DAC CLOCK : 640 MHz (LVPECL)
DATACLKP/N: 320 MHz.
Data transfer rate: 640 Mbps (DDR)
;****************************************************************** ;** DAC3484 Initialization ** ;****************************************************************** ; ; This .COE file specifies initialization values for a block ; memory of depth=64, and width=32. ; Values are specified in hexadecimal format: ; 8 MSB = address, 16 LSB = data. ; ; Loading from ROM stops when address 0x1F has been processed. ; therefore this register must be the last entry in this file. ; memory_initialization_radix=16; memory_initialization_vector= 00F29F, 01150E, 0270C2, 03A000, 040000, 050000, 060000, 070FFF, 080000, 098000, 0A0000, 0B0000, 0C05A6, 0D85A6, 0E05A6, 0F05A6, 100000, 110000, 120000, 130000, 140000, 150000, 160000, 170000, 182808, 190440, 1A0020, 1B0800, 1C0000, 1D0000, 1E4444, 1F4440, 202201, 210000, 221B1B, 23FFFF, 240000, 257A7A, 26B6B6, 27EAEA, 284545, 291A1A, 2A1616, 2BAAAA, 2CC6C6, 2D0004, 2E0000, 2F0000, 300000;
Attachments: Block Diagram of DAC interfacing, DAC register values.
Please provide some technical help on issue above.
