AD12D1600RF to Xilinx Virtex7 FPGA Constraints

Hello Evan,
We are looking into this issue. We will get back to you shortly with our feedback.

Hello Evan,

You will need to post this question to your local Xilinx/Vivado representative to get the best answer. If you can meet the setup and hold times posted in the ADC12D1600RF datasheet (500ps typical) then you will be able to close timing and capture data properly.

Hi Luke,

I thought that might be the response for the constraints question. I have also been working with a Xilinx FAE on that as well but was hoping to get some input from TI from your experience with these interfaces.

Can you provide any information on why the TI design packages for the reference boards do not include any constraints on these interfaces? The ucf provided includes LOCs and IOSTANDARDs for the pins and PERIOD constraints for the clocks but no OFFSET constraints from the LVDS inputs. Without the OFFSET constraints I don't know that the timing of this interface is properly analyzed for the setup and hold times in the datasheet.

Thanks,
Evan

Hi Evan

Unfortunately we don't really have FPGA design resources available who are familiar with this older board FPGA design. I did find one previous response from the FPGA designer related to the specific question of constraints and that is copied here:

" Input clock goes to DCM and then it samples data. DCM is set to source synchronous. Moreover, SI on the board is very good, and it preserves timing from ADC (clock to data edge and jitter). According to me in this scenario, putting setup offset time is optional. One would definitely need it if clock does not go to DCM and samples data directly."

Beyond this, I think the Xilinx experts are probably your best bet. Feel free to share the design package source code with them and let us know if you have any device specific questions that come up.

Best regards,

Jim B

Hi,

I'm going to join this thread since I'm going down a similar path to Evan, but am not quite up to where he is.  I am evaluating several devices to interface to the ADC12D1600QML, the first being the Virtex 4 (on the evaluation board), then my own target board which will use the Virtex 5 and perhaps another device, also.  I plan to use this device at 1 GSPS, with a 1:2 demux.

I have been going through the FPGA files that I have (not sure if they are current, we're working on that) and it was not clear exactly how timing will be guaranteed to be met. So a few rookie questions.

What is the configuration for the TI evaluation board?  Is the phase 0 or 90 degrees?

In the device specification, there are *typical* setup and hold times for the 90 degree phase case.  What are the guaranteed numbers?  I am working to put together a timing budget.

If I'm running at a slower than maximum rate, say 1 GSPS, then will each edge of DCLK be centered in the nominal 2 ns window where the data will be stable?

It seems that if I'm running in the 0 degree DCLK case, then the data will not be more than +/- 50 ps from the clock transition.  Then, assuming a careful matched layout of path length on the board, can I have the DCLK arrive at the flip-flop 1 ns later (about the middle of the nominal data stable period) than the data for good timing margin be doing very careful FPGA timing analysis (and hope the tools run true)?

Do I need to dynamically adjust the clock arrival time with the test pattern mode on to find the "edges" of good sampling time and then target the middle of this stable period?

Again, rookie questions, and am just getting up to speed here. So thanks for your patience.

Rich 

Hi Richard

Here are answers to your questions.

In the EVM the ADC is configured for 1:2 demux, 0 degree mode.

In 0 degree mode the data and dclk edges stay aligned within the Tosk skew tolerance which has a typical range of +/-50ps.

In 90 degree mode the DCLK edge is centered in the middle of the data eye with some variation as quantified in the Tsu and Th parameters. As the clock rate is reduced this relationship is held, with the edge remaining centered.

If you need min/max values at 1600 MHz clock rate I would use the following conservative values based on worst case design simulations:

• 1:2 demux, 90 degree mode - Tsu_min = Th_min = 425ps
• 1:2 demux, 0 degree mode - Tosk_max = 200ps, Tosk_min = -200ps

Slower clock rates will add directly to the timing margin.

It should not be necessary to dynamically sweep the clock to find the center of the data eye.

Best regards,

Jim B

Hi Jim,

Thank you very much for the information, it is helpful, and I shall continue to work through the baseline FPGA design and work on my own FPGA application.

Have a good ____________,

rich :-)