• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 45 subscribers
  • Views 485 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1299 /CS During RDATAC Mode

Arthur LAMBERT
Prodigy 110 points
Other Parts Discussed in Thread: ADS1299Hi Ryan,

So I was able to read the EEG signal quite easily. Now I had a GPIO to check the value on DRDY signal to be able to read properly the signal (because I am currently using the RDATAC mode).

My ads1299 is currently setup to have only one channel so I read data per block of 6 bytes ( 3 dummy bytes which are status register + 3 bytes of data from the channel. I am using a select/poll syscall on DRDY to know when I need to read the value from the ads1299.

Current issue is that the ads1299 does not send data at all after few minutes of recording without issue ( nothing on DRDY, or MISO).

By checking the datasheet of the ads1299, I am not sure about the CS value when I check page 36. Do I have to keep the CS value during all the record ? Currently the CS is going LOW and HIGH between each read of 6 bytes.

Thanks & Regards,
Arthur.
  • 0
    TI__Guru 66466 points

    Hi Arthur,

    When /CS is taken high, SCLK and DIN are ignored and DOUT will enter a high-impedance state. The /CS pin has no effect on /DRDY. Assuming that START remains high, the modulator will continue converting and /DRDY will still pulse at the data rate.

    You mentioned that only one channel is currently active. I assume the others are powered down? Even so, the data output sequence remains the same: 24-bit STATUS followed by 8x24 bits of channel data (216 bits total). You must read all 216 bits of data between each /DRDY pulse. /CS will have to remain low the entire time while you send 216 SCLKs. /CS must be brought low 6ns before the first rising edge of SCLK and should remain low for an additional 4*tCLK after serial communication is finished.

    Best Regards,