ADC12J4000 pll_locked status issue

Florian Stercq

Prodigy 170 points

Hi,

On our own board, we use several ADC12J4000 connected to a FPGA.

We are able to synchronize the JESD204 links and make acquisitions without problem at 4GHz.

However the PLL_LOCKED status bit (reg 0x205 : JESD_STATUS) is always stuck to '0' for all the ADCs.

The quality of the clock in input of the ADC is very good with a differential input level of 0.8Vpp.

We tested various clock frequency between 1.5GHz and 4GHz, PLL_LOCKED bit is always down.

Do we have to worry about this status while everything is working properly?

Any idea of what could cause this issue?

Kind regards

Florian

over 10 years ago

0 Jim Brinkhurst1 over 10 years ago

TI__Mastermind 44680 points

Hi Florian

The PLL_LOCKED status bit will only be set in the modes where the P54 bit (Register 0x202, Bit 7) is also set. Many of the device operating modes do not utilize the 5/4 PLL, and in those modes the PLL_LOCKED status bit is expected to be 0.

Best regards,

Jim B

0 Florian Stercq over 10 years ago in reply to Jim Brinkhurst1

Prodigy 170 points

Hi Jim,

Indeed we don't use the 5/4 PLL which explains why the PLL_LOCKED status bit is not set.

Thank you for your help.
Best regards,
Florian

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ADC12J4000 pll_locked status issue