Trigger captured using TSW14J56 and ADC12J4000

Thai,

Can you send me the ini file? By default, SYSREF is not currently used by the ADC on this evm and this may be the problem. Since the GUI does a new synchronization everytime a capture is issued, the time for synchronization to occur will vary. I will get more information for you regarding this setup.

Regards,

Jim 

Jim, here is my ini file.

[ADC]

Interface name="TSW14J56_MC_FIRMWARE"
Number of channels=1
Channel Pattern=1
Data Postprocessing=0
\\operation:operand
\\operaion
\\0=bit shift
\\1=xor
\\2=and
\\3=or
\\4=not
\\operand
\\value(+ve if bitshift by right and -ve if bitshift by left)
\\E.g 0:-2,1:1024
\\bitshift by left 2 times and then xor by 1024
Number of Bits=12
Max sample Rate=4000000000
Register_Config="-"
\\[Register Address]:[Register Value]:[Number of Bytes to be sent as]
DLL Version=1.0
Read EVM Setup Procedure="EVM Setup Procedure not available"
\\use <> as delimiter for newline

[Version 1.0]

JESD IP Core_CS=0
JESD IP Core_F=1
JESD IP Core_HD=1
JESD IP Core_K=32
JESD IP Core_L=8
JESD IP Core_M=4
JESD IP Core_N=16
JESD IP Core_NTotal=16
JESD IP Core_S=1
JESD IP Core_SCR=1
JESD IP Core_Tailbits=0
JESD IP Core_LaneSync=1
JESD IP Core_Subclass=1
JESD IP Core_JESDV=1


Sysref Based Master Slave Trigger = 1
Is Capture Trigger SMA = 1

MIF Config= 0.611G to 0.875G:RX:RX_PMA_x5,0.875G to 3.90625G:RX:RX_PMA_x10,3.90625G to 10G:RX:RX_PMA_x40
\\List of Lane Rate Range,PLL Type and their MIF File names that needs to be configured,separated by ":"
\\These MIF Files need to be present under MIF Files Folder
Fabric PLL Counter = 0.611G to 0.875G:0x080404,0.875G to 3.90625G:0x080808,3.90625G to 8G:0x080202
Invert Sync Polarity = 0
\\Invert Sync polarity, 1:invert; 0: do not invert
Invert Serdes Data = 1
\\Invert Serdes Data, 1:invert; 0: do not invert
Transceiver Mode = 0
\\1:xcvr mode; 0: TX/RX only mode
Lane Mapping=lane0:0,lane1:1,lane2:2,lane3:3,lane4:4,lane5:5,lane6:6,lane7:7
\\Lane pattern for the LMF modes
Group 128 bits Flag = 1
\\If 1, will group 128 bits from each DDR, and then apply the channel pattern
\\If this parameter is not present, it will follow the earlier mode used in v2.40
Bit Packing = 1
\\0 - Data are not bit packed.
\\1 - Data are bit packed(MSB aligned) without any padded zeroes
Bit Packing Channel Pattern =C1S1[11:4],C1S2[11:4],C1S1[3:0],C1S9[11:8],C1S2[3:0],C1S10[11:8],C1S9[7:0],C1S10[7:0],C1S17[11:4],C1S18[11:4],C1S3[11:4],C1S4[11:4],C1S3[3:0],C1S11[11:8],C1S4[3:0],C1S12[11:8],C1S11[7:0],C1S12[7:0],C1S19[11:4],C1S20[11:4],C1S5[11:4],C1S6[11:4],C1S5[3:0],C1S13[11:8],C1S6[3:0],C1S14[11:8],C1S13[7:0],C1S14[7:0],C1S21[11:4],C1S22[11:4],C1S7[11:4],C1S8[11:4],C1S7[3:0],C1S15[11:8],C1S8[3:0],C1S16[11:8],C1S15[7:0],C1S16[7:0],C1S23[11:4],C1S24[11:4],C1S17[3:0],C1S25[11:8],C1S18[3:0],C1S26[11:8],C1S25[7:0],C1S26[7:0],C1S33[11:4],C1S34[11:4],C1S33[3:0],T[4],C1S34[3:0],T[4],C1S19[3:0],C1S27[11:8],C1S20[3:0],C1S28[11:8],C1S27[7:0],C1S28[7:0],C1S35[11:4],C1S36[11:4],C1S35[3:0],T[4],C1S36[3:0],T[4],C1S21[3:0],C1S29[11:8],C1S22[3:0],C1S30[11:8],C1S29[7:0],C1S30[7:0],C1S37[11:4],C1S38[11:4],C1S37[3:0],T[4],C1S38[3:0],T[4],C1S23[3:0],C1S31[11:8],C1S24[3:0],C1S32[11:8],C1S31[7:0],C1S32[7:0],C1S39[11:4],C1S40[11:4],C1S39[3:0],T[4],C1S40[3:0],T[4]
\\Channel and Sample number starts from 1. Bit numbering starts from 0
\\Tail bits are specified by T[No of Tail Bits]
\\Channel pattern should be formed as the data will be in transceiver mode.
\\(i.e) In RX only mode, take 128 bits from DDRA, 128 bits from DDRB,followed by next 128 bits from DDRA, etc..

Thai, Jim, I split this thread into a new forum post so that it will get tracked properly.

Ken

Hi Thai

The default configuration files for the ADC12J4000EVM has the SYSREF clock to the ADC turned off. I can send you some register configuration files that will enable SYSREF output from the LMK04828 and SYSREF processing in the ADC.

The files I will send are specific to the DDC mode, clock source and sample rate.

Given the earlier information you sent I assume you are using the raw 12 bit DDC bypass mode of operation. Please let me know if this is incorrect.

Can you confirm what sample rate (DEVCLK frequency) you are using?

Are you using the onboard clock source, or external clocking?

Best regards,

Jim B

Hi,

I am also having problems with trigger performance using external trigger source on TSW14J56EVM with ADC12J4000EVM. It seems that on some of the captures that I take start time of acquisition has a large offset. I am not trying to make a simulataneous capture on two master-slave boards, just a capture on single board on external trigger. Is this also related to the SYSREF configuration? Thank you for any insights.

Also, is there any specification on jiter in trigger activation time?

Hi Jurgis

Sorry for the delay getting back to your latest post.

How much time do you define as a large offset from trigger application to capture of the ADC data?

The trigger based system is mainly intended to allow synchronizing multiple boards, and to give outside control over data capture. It is not optimized for low latency response to trigger.

Best regards,

Jim B

Jim,

I am having similar issue as Jurgis does. There has always been an unrealistic delay between the external trigger and the arrive of the expected waveform.

Can you provide some insight what kind latency and jitters are expected using TSW14J56EVM trigger in? Also do you have any suggestion if we hope to have low latency response to external trigger?

Thanks, Bing

Hi Jurgis and Bing

The TSW14J56 firmware receives the trigger input, and then waits until the next Start of Multi-Frame before initiating the storage of data. Given the firmware architecture we use in the TSW14J56EVM it isn't possible to start buffering data at arbitrary times, it must begin at Start of Multi-Frame.

If the Trigger pulse is asynchronous to the JESD204B Multi-frame, there will be variable delays. The variation will be a maximum of K frame periods for the ADC mode in use, where K is the number of Frames per Multi-Frame. The frame period in time can be calculated as:

T_Frame = (F * 10) / Fbit where F is the number of Octets per Frame, and Fbit is the bit rate of the JESD204B data interface. After 8b10b encoding there are 10 bit-times per octet, so there are F * 10 bit-times per frame.

I hope this is helpful.

Best regards,

Jim B