DAC7760 SPI-CRC Interface

Cafain,

My apologies for the delay in responding to this thread. The E2E was going through some updates at the time and it seems I did not receive a notification about this post.

The DAC7760 SPI interface will latch the last 24 or 32 bits, depending on whether the CRC mode is enabled or not, that it "saw" on the SPI bus upon a rising edge on the LATCH pin.

cafain said:

1) When DAC was in the state set as 32Bit with CRC, and 24Bit data was written in from MCU, does a problem occur to movement of DAC?

If somehow the last 32 bits written to the bus happened to be a valid 24-bit word / 8-bit CRC combination the DAC would latch the word. This is extremely unlikely, though. In all likelihood the part would reject the input word since the 24-bit data would not match the 8-bit CRC value and raise the corresponding ALARM condition.

cafain said:

2) When DAC was in the state set as 24Bit which isn't with CRC, and 32Bit data was written in from MCU, does a problem occur to movement of DAC?

In this case no matter what the part is going to latch the last 24-bits. If those 24-bits happen to be a valid write, the part will take action on the data written to the bus.