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In regards to ADS1274 D-FlipFlop, SCLK, do we need latch for SM320F28335

richard payne
Genius 4640 points
Other Parts Discussed in Thread: ADS1274

In regard to ADS1274 D-FlipFlop, SCLK discussion. I wish to establish if the circuit really need latch for SM320F28335?

Below is the connection configuration

ADS1274                        SM320F28335 (McBSP)

SCLK(28)                        MCLKRA     (This is FMOD source for ADS1274)

CLK(27)          ->             MCLKRA     (SCLK and CLK tied together)

FSYNC(29)     ->             MFSXA

TDM(20)         ->             MDRA

                                       MDXA = NC

                                       MFSRA = NC

                                       MCLKXA connect to external clock

Configure for TDM, FSYNC, LOW POWER or HIGH RESOLUTION (VIA jumper resistor). 

I have 3KHz with 12KSPS or 24KSPS (configure FMOD clock close to 3MHz or 6MHz  from MCLKRA)

Do I need latch?, can you shown me if this violate timing or not.

On seperate topic.......I have CH1 and CH2 only (CH3 and CH4 disabled), should I use fixed data or dynamic so I do not need to accept CH3 and C4.

  • 0
    TI__Guru 66466 points

    Hi Richard,

    I addressed this question in another E2E thread. Please let me know you still have doubts about the need for the D flip-flop.

    Regarding your other question, I think it makes more sense to use the dynamic mode for data output. This would require sending fewer SCLKs and would reduce the minimum SCLK speed requirement. Keep in mind that new data will become available at the same rate - but you will have less data to read out with dynamic mode. :)

    Best Regards, 

  • 0 in reply to Ryan Andrews
    Genius 4640 points
    Okay for FCLK/CLK <15MHz, the latch may not be needed under framesync mode, it depends how you tolerate margin between SCLK rising edge and delayed DOUT.