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ADS1293 SPI data frame format and clock speed

Sergio
Expert 3835 points

This discussion is carried over from another thread into this dedicated thread.

chandrashekar reddy said:

long back we have discussed about interfacing of ADS1293 EVM with external controller through SPI port, i have interfaced and wrote program for the same i am getting junk data, can you please let me know the clock speed of the ADS1293 SPI port and as well let me know the data frame format, format of the data sent by the ADS1293EVM.

 

  • 0
    TI__Expert 3835 points

    Hi Reddy,

    SPI clock

    The maximum SPI clock speed of this device is 20 MHz. The minimum SPI clock speed required will depend on the amount of data to read from the device and the output data rate (conversion rate).

    If you use the Streaming mode described in section 8.5.6 of the datasheet, the SPI operation will require 8(1+N) SPI clock cycles, where N is the number of data bytes to read. Each ECG channel, for example, consists of 3 bytes of data. In the Streaming mode, all the data enabled for loop-read in register 0x2F is read from register 0x50 by performing a read operation with an extended CSB assertion.

    Suppose that the output data rate is 200 samples per second and you wish to read ECG data from channel 1 and 2, which will amount to 6 bytes of data per sample cycle. The CSB assertion to low should be extended for 8(1+N) = 8(1+6) = 56 SPI clocks.

    In order to read the data before new data overwrites it, the SPI clock should run faster than 200*56 = 11.2 kHz. The availability of new data is indicated by the falling edge of the DRDYB line, which is intended as an interrupt signal to the micro.

    Now, depending on what the micro is going to do with the data after a frame is read, the SPI clock speed would need to be faster to allow for the processing to take place before new data is available.

    Frame format

    The format of the data during in Streaming mode is by incremental address. Depending on the channels enabled for loop read back mode in register 0x2F, the data read from register 0x50 will correspond to those channels' data registers in incremental mode. Continuing with the example, if ECG channels 1 and 2 are selected in 0x2F, the data read back on SDO will be ordered follows: ecg1_upper_byte, ecg1_middle_byte, ecg1_lower_byte, ecg2_upper_byte, ecg2_middle_byte and ecg2_lower_byte. The order of the bits inside each byte of data is MSB first and LSB last.

    The micro should concatenate the three bytes of data per channel into a 24 bit number. ecg1_upper_byte will correspond to bits [23:16], ecg1_middle_byte will correspond to bits [15:8] and ecg1_lower_byte will correspond to bits [7:0].