ADS42LB49EVM syncing

user4166913

Other Parts Discussed in Thread: ADS42LB49

Is it possible to sync test patterns of two ADS42LB49 ADCs using syncin line? Datasheet says very little about sync feature. Also in earlier version of datasheet register 0x30 was documented and in recent version it is missing. Is this functionality gone? I need this feature to synchronize multiple ADC for simultaneous sampling and to realign the data inside FPGA.

Old datasheet:

http://datasheet.octopart.com/ADS42LB49IRGCT-Texas-Instruments-datasheet-14540160.pdf

New

http://www.ti.com/lit/ds/slas904e/slas904e.pdf

over 10 years ago

0 Ebenezer Dwobeng over 10 years ago

TI__Genius 9695 points

Hi,

The sync pin is used to synchronize the clock divider of the input clock (CLKINP/N) in multiple ADS42LB49. This is only needed if the clock dividers are set to a value greater than 1. Please refer to block diagram on pg 1 of datasheet. No mechanism exist to synchronize internal test pattern generated by two ADS42LB49. However, the analog input signal to multiple ADCs can be synchronized with the sync pin. I have requested for information on register 0x30 and will update you later on.

Thanks,
Eben.

0 Ebenezer Dwobeng over 10 years ago in reply to Ebenezer Dwobeng

TI__Genius 9695 points

Hi,

Thanks,

Eben.

0 user4166913 over 10 years ago in reply to Ebenezer Dwobeng

Prodigy 125 points

Just to clarify. There is no way of synchronising those ADCs?
Thanks,
Rafał

0 Ebenezer Dwobeng over 10 years ago in reply to user4166913

TI__Genius 9695 points

Hi Rafal,

The ADCs can still be synchronized just that the sync enable bit no longer exists or is required to synchronize the ADCs.

Thanks,

Eben.

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ADS42LB49EVM syncing