Hi,
I am trying to interface to this reference board using a Xilinx Virtex VC707 evaluation board over FMC bus. The main design of your board interfaces to an FPGA (Virtex4) with 4 data sets of DI+, DID+, DQ+ and DQD+ buses. This FPGA has only a single clock input from this ADC called DCLK. The Virtex4 outputs 4 buses of the reduced clock data streams of FMC_DI, FMC_DID, FMC_DQ and FMC_DQD connected to the FMC bus at 375MSPS. Instead of a single clock at the FMC there are now 4 clocks each corresponding to the data steams names. In order to latch this data must I use all 4 clocks and collect 4 data streams synchronized to each using rising edges? Then reassemble them in byte order? Is this how it is supposed to work or am I missing something?
Sincerely,
Dan Dahl
