Inquiries regarding ADS1282

Atsushi Okui

Other Parts Discussed in Thread: ADS1282, ADS1281, OPA1632, PCA9535, TINA-TI, DAC1282

Hello, all

Now we have some inquiries regarding ADS1282 from our customer.

Please refer to the items below, and feedback us with your comment.

Q1. When referring OUTPUT SPECTRUM on datasheet page 7, we found high frequency distortion (Amplitude down to 0dB) on 30Hz. Please let us clarify whether this could be reduced by some method or not.

Q2. When inputting single ended signal source in front of this device, please let us clarify whether we should put "single end to differential conversion" circuit or not.

Q3. When referring "Figure 70. Geophone Interface Application" on datasheet page 42, external diode clamps are described in front of AINP1 and AINN1 pins.

Please let us clarify whether you have any limitation for capacitance on each diodes.

Q4. Since we are considering to have accurate time synchronization for SYNC pin, we assume that the maximum CLK frequency is 4.096MHz. However, please let us clarify how we could set optimized CLK frequency for synchronizing on each one second.

We thank you in advance for your information.

Best regards,

over 10 years ago

0 Christopher Hall over 10 years ago

TI__Mastermind 44680 points

Hello Okui-san,

I'll do my best to answer your questions:

Q1) I'm not sure I understand this particular question...
The OUTPUT SPECTRUM figures were measured with an applied 31.25 Hz signal, hence the signal amplitude is nearly 0 dB at this frequency. This is not a distortion; removing the input signal would remove the fundamental frequency. The visible distortions are only the harmonics, but THD performance is still about -120dB.

Q2) The ADS1282 is intended to be used with a fully-differential input signal, but it can also be used with a single-ended input signal. In general, fully-differential signals will have better SNR and THD performance because of their common-mode noise rejection (refer to the blog post: Performance comparison between SAR ADC input types – Part 2).

The decision to add a single-ended to differential conversion circuit is a difficult judgement call and will depend on the implementation:

- If you think the signal will be susceptible to additional common-mode noise in your circuitry (or if it will go through additional signal conditioning prior to the ADC), it may be worthwhile to do this conversion first. The conversion circuit would need to use a fully-differential amplifier (NOT the two op amp single-ended to differential conversion circuit, because the two op amp circuit creates two signals with mismatched phases).
- However, adding the single-ended to differential conversion circuit will also add some noise to the signal. Therefore, if the signal path to the ADC is short, it may be better to skip the single-ended to differential conversion.

Q3) I am not aware of a capacitance limitation for the external diode clamps. Usually the more important specification for these components is the leakage current. The leakage current should be keep to a minimum as it interacts with the filtering resistors and causes measurement errors that will vary over temperature.

Q4) Using a 4.096 MHz CLK should be fine. You could look into using the continuous-sync timing and apply a 1Hz clock to the SYNC pin (derived from the 4.096 MHz CLK) to keep the devices synchronized. If you're synchronizing across multiple channels, make sure CLK is shared between multiple ADS1282's with matched trace lengths.

Best Regards,
Chris

0 Atsushi Okui over 10 years ago in reply to Christopher Hall

Genius 4015 points

Hello, Hall-san,

Thank you for your prompt reply.

With regard to the inquiries regarding ADS1282,we have some additional inquiries from them.

Please refer to the items below, and feedback us with your comment.

Q5. When referring "Figure 70. Geophone Interface Application" on datasheet page 42, 75kohm resistors are added in front of CAPN (pin 13) and CAPP (pin 14). I assume these resistors are aimed for adding 20mV offset to make idle tone outside of pass bandwidth. However, our concerning is whether this makes reduction on dynamic range since this applies the DC level voltage on differential input.

Meanwhile, when referring the schematic of ADS1281/82EVM on page 29 of "ADS1282EVM and ADS1282EVM-PDK User's Guide", only "10nF C0G" is placed between CAP+ (pin 13) and CAP- (pin 14).

Please let us clarify whether this difference between each above has some influence on the performance of ADS1282 or not. Also, please let us clarify which pin is CAPN(CAP-) or CAPP(CAP+).

Q6. When referring "Figure 70. Geophone Interface Application" on datasheet page 42, we found 100ohm resistors (R1 to R4) and 10nF capacitor (C4). We assume that this differential filter is aimed for low pass filter not anti-aliasing for input signal and depending on sensor type we use.

Since we would like to make sure how to calculate correct cut off frequency, please let us clarify how we could find out any formula.

We assume that the cut off frequency when using these components would be 39.7KHz, based on R=Xc=400ohm.

Q7. Please let us clarify whether you have any recommended DAC for generating test signal for ADS1282.

Q8. When referring "Table 16. Offset Calibration Values" and "Table 17. Full-Scale Calibration Register Values" on datasheet page 30, we understand that OFC and FSC registers are 24bit. Please let us clarify whether the last 8bit of 32bit are not compensated.

Q9. Since ADS1282 does not have GPIO pin, please let us clarify whether we could add GPIO expander on serial output lines.

Q10. When referring "CONFIG0 : CONFIGURATION REGISTER 0 (ADDRESS 01h)" on datasheet page 37, we understand that FIR Phase Response could be selected on either Linear phase or Minimum phase. Please let us clarify wheter we could select our own coefficient for FIR filter.

We thank you once again for your information.

Best regards,

0 Christopher Hall over 10 years ago in reply to Atsushi Okui

TI__Mastermind 44680 points

Hi Okui-San,

Certainly!

Q5)

The 75 kOhm series resistors (in Figure 70) are indeed there to add a small DC offset to the ADC input (which moves the modulator tone outside of the digital filter passband - please refer to the "Modulator" section on page 16 of the datasheet for more information about this tone!). The ADS1282EVM did not incorporate the circuitry shown in Figure 70, as it is optional.

While this would only slightly reduce the ADC's input dynamic range (for a positive differential input), performing an offset calibration would make the full input dynamic range available again!

Please note that the ADS1282EVM-PDK User's Guide schematic mislabeled pins 13 & 14. The ADS1282 data sheet is correct (pin 13 is CAPN, pin 14 is CAPP, the negative and positive PGA outputs, respectively).

Q6)

The filter shown in Figure 70 provides both common-mode and differential signal filtering. The cutoff frequencies are given by the equivalent RC filters for each mode. Here is the standard form of this filter with the equations for the cutoff frequencies:

For the exact cutoff frequencies of the filter in figure 70, you’ll need to run a simulation to figure it out. The equation is not so simple because the second filter stage will have a loading effect on the first filter stage. You’ll also find that resistors R3 and R4 will further reduce the differential cutoff frequency, without reducing the common-mode cutoff frequency (ignoring the loading effects).

Q8)

Correct! Think of the offset calibration register bits as only adding to the 24 most significant bits in output code. (The last 8 bits of the output code will be fairly noisy; therefore, adding to these bits wound not have as much effect on the offset).

For the Full-scale calibration, the gain correction is simply the ratio of the FSC[0:2] register value to 400000h.

Q9)

I’m not exactly sure what you mean. Are you referring to a /CS pin or just adding GPIO’s?

For the “/CS” topic refer to the FAQ: Where is the "/CS" pin?.
If you just need extra GPIO pins, then you would add the GPIO expander to your MCU.

Q10)

The FIR coefficients are hard-coded. If you want to implement your own FIR filter, then you would set the ADS1282 to SINC filter mode and post-process the data in your MCU or DSP (Note: The FIR filter is in series with the SINC filter).

Best Regards,
Chris

0 Atsushi Okui over 10 years ago in reply to Christopher Hall

Genius 4015 points

Hello, Hall-san,

Thank you for your continuous support towards the inquiries regarding ADS1282 from our customer.

We would appreciate if you could let us know about your recommendation on Q7.

In addition to above items, we have some additional inquiries from them.

Please see the items below, and feedback us with your comment.

Q11. When referring "10 Running the Software and Completing Driver Installation" on page 13 of "ADS1282EVM and ADS1282EVM-PDK User's Guide", we understand that this EVM does not support Windows Vista.

However, since WIndows XP is no longer supported, please let us clarify whether Windows 7 is supported for this EVM or not.

Q12. When referring following E2E thread, we understand that MMB motherboard is no longer available/supported.

http://e2e.ti.com/support/dsp/c5000/f/109/t/351879

However, since we are willing to debug from PC for controlling whole system, please let us clarify whether you have some good alternate idea to have easy method for debugging.

Q13. When referring the schematic of ADS1281/82EVM on page 29 of "ADS1282EVM andADS1282EVM-PDK User's Guide", we could find out OPA1632 as U4 and U5.

We assume that these OpAMPs are included in filtering which is answered on Q6. Please let us clarify whether we could simulate whole cutoff frequencies for this circuit as well.

Also, please let us clarify the purpose that REF5025 is placed as U2 and PCA9535 as U7.

Q14. With regard to your answer on Q6, we could not find out TINA-TI model for ADS1282. Please let us clarify whether you have any idea to have simulation on another tools.

Q15. We would appreciate if you could provide us some guidelines for the pattern layout when using this device. Please let us know whether such documentation is available first.

Q16. When referring the schematic of ADS1281/82EVM on page 29 of "ADS1282EVM and ADS1282EVM-PDK User's Guide", we could find out that OPA1632 (U4 and U5) are +/-10V supplied but ADS1282 is +/-2.5V supplied.

Please let us clarify whether the 8 diodes (BAT54S) are placed for protection in case the voltage for analog inputs on ADS1282 exceeds the voltage level which is described on ABSOLUTE MAXIMUM RATINGS on the datasheet.

We thank you once again for your information.

Best regards,

0 Christopher Hall over 10 years ago in reply to Atsushi Okui

TI__Mastermind 44680 points

Hi Okui-san,

Opps, I skipped over question 7...

Q7) We recommend the DAC1282.

For your other questions:

Q11) Windows 7 is supported.

Q12) The MMB0 is still available and it comes with the ADS1282EVM-PDK. Regarding MMB0 support, we'll provide the MMB0 and can share the schematics with you; however, there is no User's Guide specific to the MMB0, and we do not provide MMB0 support if you were to modify the MMB0 for your own development

Q13) Yes, you could simulate the OPA1632 circuit used on the ADS1282EVM. The SPICE model for the OPA1632 can be found at this URL:

Q14) We don't have any SPICE models for our delta-sigma ADC's. Only recently have the SAR ADC SPICE models (of the analog front-end only) become available. The ADS1282 has a high impedance input because of the integrated PGA; therefore, it is very easy to drive. In most cases you can connect the sensor directly to the ADS1282 (with some additional RC filtering at the input, of course).

Q15) Refer to page 54 of the ADS1282 data sheet for the PCB footprint.

Q16) Yes, the input diodes help to prevent input over voltage to the ADS1282. However, I did not design this circuit nor have I fully tested the input protection capability. If you get an ADS1282EVM, I would recommend you evaluate this circuit to see if it would be sufficient for your application. I f you do, I would be interested to hear about your findings! So far, I have not heard any complaints from others who have used the ADS1282EVM.

Best Regards,
Chris

0 Atsushi Okui over 10 years ago in reply to Christopher Hall

Genius 4015 points

Hello, Hall-san,

Thank you as usual for your continuous support towards the inquiries regarding ADS1282 from our customer.

In addition to above, I have some additional inquiries from them.

Please refer to the items below, and feedback us with your comment.

Q17. When referring following E2E thread, we understand that Resolution 31bit is not proven and the user could stop clocking out data after 24 bits.

http://e2e.ti.com/support/data_converters/precision_data_converters/f/73/p/57539/204615#204615

Please let us clarify whether this means that the resolution (not dynamic range) on this device is at least 24bit or not.

Q18. With regard to your answer on Q1, please let us clarify whether the summation of high frequency on 31.25Hz is converted into -120dB as THD. Also, we assume that the figure described on datasheet page 9 also shows idle tone even though the case of fixed DC input.

Q19. We would appreciate of you could show the method of each settings from power up to data acquisition, and easy flow chart of offset and full scale calibration.

Please let us know whether such documentation would be available.

Q20. When referring following E2E thread, we understand that some customers prefer to apply a continuous clock to the SYNC pin to keep multiple ADS1282 's in a "lock-step" operation.

http://e2e.ti.com/support/data_converters/precision_data_converters/f/73/p/329630/1161956#1161956

On our case, we need to syncronize same ADS1282s which are placed on another PCB by１Hz. Also, the accuracy is very critical on this synchronization. Please let us clarify whether SYNC pin could be used for compensation on our software on this case.

If possible, please let us clarify whether we could use maximum frequency (4.096MHz) for this synchronization.

Q21. With regard to your answer on Q8, we could understand that the last 8bit of 32bit are not compensated.

However, the specified dynamic range (123dB) for this device could be kept on 20bit. Please let us clarify whether 123dB is still maximum value for 24bit or could be increase up to 144.5dB.

We thank you once again for your information.

Best regards,

0 Christopher Hall over 10 years ago in reply to Atsushi Okui

TI__Mastermind 44680 points

Hi Okui-san,

Q17)

The ADS1282's noise performance specifications are shown on page 31 of the datasheet as SNR, because this device is intended for AC applications. If you are more interested in the DC performance, you can use Equation 1 to convert the SNR value to an input-referred noise and derive the DC specifications.

From a DC perspective, you'll see that output code bits 0-7 are very noisy, and the more significant bits (15-30) are fairly stable. If noise-free bits are what you care about in your application, then the 24 most significant bits of data may be all you care about. However, if your application samples an input many times to find an average, then the 31-bit data will be useful to you for averaging. Bits 0-7 provide you with (typically) Gaussian noise that can be average to increase the resulting resolution. Refer to the blog: How to use thermal noise to your advantage.

Q18)

THD is the ratio of the "sum of signal harmonic amplitudes" to the "signal's fundamental amplitude". This would not include the idle tone.

Yes, the idle tone is present even with a dc offset, however it is shifted out-of-band. Therefore, you can only see the tone when you look at the modulator' output spectrum (before the ADC's digital filter). Once the data is processed by the digital filter, the idle tone will gone. For example, the idle tone is seen in figure 37 but not in figures 1-10.

Q19)

I don't have such a diagram or document. This sequence of operations will likely be very specific to your application. If you have additional questions about start-up or calibration I can try to answer them!

Q20)

Whether or not the ADS1282's are on the same PCB as your MCU, you'll need do you best to match traces lengths from the MCU to all ADS1282 devices. Also, the 4.096MHz clock should be shared to each ADS1282 and in phase. Therefore, matching traces lengths from the clock to each ADS1282 is also important for synchronization. Those are the most important considerations for synchronizing these devices.

Since the SYNC pin only requires one trace, it may be easier to match the SYNC pin trace lengths and use the SYNC pin, instead of the SYNC command. Then, assuming your layout keeps all ADS1282 signals in phase, you may consider applying a continuous SYNC pulse to keep all of the devices in phase (in case of a clock glitch on one device, for example). The SYNC pulse needs to be a multiple of the data rate! Therefore, you CANNOT apply the 4.096MHz clock to the SYNC pin!

Q21)

You are referring to the 123dB spurious-free dynamic (SFDR) range? SFDR is the ratio of a fundamental signal to the largest spurious signal. This is an AC performance metric and not really related to the DC calibration.

If instead you're referring to the dynamic range. This would be the ratio of the largest measurable signal to the smallest resolvable single. This is dependant on the noise and also not related to calibration.

Best Regards,
Chris

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