Hello,
I'm using the ADC128S102QML. In my design I'm driving mumerous analog DC signals through MUX devices to a buffer which is driving the ADC .
The sequence is as follows (and repeats cyclicly for a number of inputs):
step 1 - External Mux switching (to deliver the respective input to the ADC).
step 2 - settling time (I can change the settling time from 10usec-80usec).
step 3 - ADC sampling (SPI activated).
Note: The MUX are switched ( back to step 1) immediately after the 16 SPI clock cycles are done.
I'm having some issues that I'm trying to figure out:
When sampling consecutive signals with different voltage levels through an external MUX (voltage step on the ADC input) , the adc returns inaccurate results.
first I thought that it was a problem of settling time of the input circuitry. however, lengthening the time between each convertion (10usec, 20usec, ... ,80usec) did not affect the result. All gave very stable results (yet inaccurate). Even If I initiate a single sample convertion long after the last convertion has been made (seconds), the answer would be inaccurate. that is if the previous sample is of a significantly different voltage level.
Moreover, when sampling a signal of around 4.7V I noticed that the ADC returns FFF (its Vref is 5V). Looking on the ADC input signal with a scope, the only time that the input signal passes 5V is right after sampling the 4.7V when the MUX are switched (a short spike is present on the ADC input at that time).
To my undrstanding, The ADC is in track mode in the 1st 3 SPI clock cycles, so a spike right after the 16th SPI clock cycle shouldn't have any effect... (?).
Also, when sampling twice the same input signal (External MUX is staying on the same address) or when sampling two consecutive signals that have similar voltage levels, the second sample is accurate.
Any help or insight would be greatly appreciated!
Regards,
Itai.
