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ADS1282-HT GANCAL Questions

Other Parts Discussed in Thread: ADS1282-HT, ADS1282

We are currently using ADS1282-HT and running into some problems.  After lots of research thru the forum, we are able to get the chip to read the data by command.  Currently we are stuck in the OFFSETCAL & GANCAL.  Note that we are trying to follow Figure 66 of the spec.  Plus, input MUX was set to 100 where AIN2 was connected to GND to generate the zero input for OFFSETCAL..  Here is our sequence -

1) SDATAC

2) SYNC

3) 32ms delay

4) RDATAC

5) Wait for DRDY to go low

6) ~90us (DRDY goes low)

7) SDATAC

8) OFFSETCAL or GANCAL

9) RDATAC

Here are a list of questions,

1) DRDY does not mimic what's in Figure 66.  In our system, DRDY goes low follows RDATAC command and then stays high.  Note that it only take 90us between RDATA and DRDY goes low...  Is this okay?

2) GANCAL, what is the input signal?  Does it has to be positive/negative full scale?  Or any input in between?

3) Are there SPI and DRDY waveforms on how GANCAL/OFFSETCAL is supposed to behave?

Thanks,

Ji Ye Lin

  • Hi Ji Ye Lin,

    First off, which filter mode are you using on this device SINC or FIR mode?

    From your timing measurement of RDATAC to /DRDY low, it would seem like you are running in SINC filter mode. In SINC filter mode, running OFSCAL and GANCAL will not be of benefit to you. The internal calibration block will only be useful in FIR filter mode. The calibration block is bypassed  in SINC mode (see the filter diagram below), and output data will not scale according to the OFC and FSC register data.

    To answer your other questions:

    Ji Ye Lin said:
    1) DRDY does not mimic what's in Figure 66.  In our system, DRDY goes low follows RDATAC command and then stays high.  Note that it only take 90us between RDATA and DRDY goes low...  Is this okay?

    I think this may be because you're using SINC filter mode and a CLK of about 1.6 MHz, is this correct?
    If not, then it would seem as if the ADC is not responding to your previous commands - I would then want to look at an oscilloscope or logic analyzer to make sure the SPI communication is correct.

    Ji Ye Lin said:
    2) GANCAL, what is the input signal?  Does it has to be positive/negative full scale?  Or any input in between?

    When sending the GANCAL command, the ADC expects a full-scale voltage. For example, +2.5V would be positive full scale for a reference of 5V, and PGA gain of 1 V/V. More generally, it's calculated as "+FS = +Vref / (2*PGA) ".

    If you are using SINC filter mode, you could input any input voltage within the ADC's input range and manually perform calibration within your MCU. You would simply scale the gain error factor by your input signal (as % FS).

    Ji Ye Lin said:
    3) Are there SPI and DRDY waveforms on how GANCAL/OFFSETCAL is supposed to behave?

    I don't have a screen capture of this off-hand. It should look like figure 66.

    I could review your SPI communication if you have some screenshots to share.

    Best Regards,
    Chris

  • Hi Christopher,

    I would need to confirm which mode we are running - sync filter or FIR filter mode. The data sheet is extremely confusing on the GANCAL section with respect to what input it's looking for - a input must be in the range of, but not exceed full scale!?!? Plus, the data sheets do not have any reference on the need to perform SDATAC after writing to registers, or the need to wait ~64 data conversions, etc.

    One more question, we are running pulse sinc mode, and would like to use external sync input pin prior to perform read data by command, do we still need to generate a delay (~32ms) between sync and read data by command? Please advise. Thanks.

    Regards,
    Ji Ye Lin
  • Hi Ji Ye Lin,

    I agree that the data sheet could do a better job of explaining the topics you mentioned.

    The answer to your question about the SYNC pin timing is... I'm not sure, but including the delay would be the safe option. However, you also ought to be aware of the odd behavior of the RDATA command (I say "odd" because it is different from other TI devices with the same command name).

    Most people I have supported, who are using the ADS1282, will use "RDATAC" mode when reading data. (The ADS1282 can be in either RDATAC or SDATAC mode, and sending the corresponding command will switch to that mode). Note the difference in reading data between the two modes:

    • In "RDATAC" mode:
      Data is read simply by clocking it out (sending 0x00 bytes on DIN), after /DRDY goes low.
    • In "SDATAC" mode:
      Reading data requires that you notify the ADS1282 that you want to read data BEFORE the /DRDY falling edge.Therefore, you would need to send the RDATA command, wait for /DRDY to go low, and then clock out the data (as if you were in "RDATAC" mode).

      (Most other TI devices would have you wait for a /DRDY falling edge, send RDATA, and then start clocking out data immediately).

       

    Personally, I think reading data in "SDATAC" mode is a bit of a hassle, because if you don't send RDATA before the /DRDY falling edge, you'll lose that data and have to wait until the next conversion to read out data.

    Best Regards,
    Chris

  • Hi Chris,

    Okay, I confirmed that we are running the "Sinc + LPF + HPF filter blocks" mode. Note that we set the Data Rate Select to "011: 2000SPS" and our system clock is 4MHz. Let's say we write to the control register, how long do we need to wait before we can issue a read data by command? The spec calls out for 63 data interruptions. Thus the 63 data interruptions should include both the Sinc +FIR sampling rate - calculated to be ~32.5ms. If we have a sync command after register write command, do we have to include the 63 data interruptions and the sync delay calculation per table 10? Plus, is there any delay for the HPF filter block?

    Please advise. Thanks.

    Regards,
    Ji Ye Lin
  • Hi Ji Ye Lin,

    For read data by command, you need to send RDATA before /DRDY goes low. Therefore, you would not need to wait to send RDATA. However, after sending RDATA, you would still wait for /DRDY.

    I believe the settling time will be about 64 conversion cycles or 33 ms with the HPF (note that /DRDY will remain high during this period, until data is settled). The HPF only has a single delay stage (I gather from equation 14); therefore, it should only add one more conversion cycle delay. Unfortunately, the datasheet does not specify a HPF delay, so let me double check this with a design engineer.

    From the end of the SYNC command, it will be t_DR +/- [1/ f_CLK] before /DRDY goes LOW (an uncertainty of 1 clock period). Use table 10 to determine t_DR for the FIR filter, and (for now) add 1/f_DATA to account for the HPF.

    Best Regards,
    Chris