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ADS4128 and ADS4449 clock frequency deviation

Bo Dong26
Prodigy 250 points
Other Parts Discussed in Thread: ADS4128, ADS4449

Hi,

In our application, the clock input to the ADC (ADS4128/ADS4449) is generated from a series events, so the clock frequency is not pure, say, 100MHz +/-1%. I wonder if these ADCs can work with this kind of clock input. And the last several conversions left in the ADC pipeline is negligible. Thank you in advance for the reply.

Bo.

  • 0
    TI__Genius 17340 points
    Hi Bo,

    I am still looking into this and have an open request with the design team.

    One thing of interest is whether the clock signal runs constantly, but the frequency may change slightly, or whether there will be a long period without a clock followed suddenly by a clock - with expectations that the sampling starts right on that first clock edge.

    Regards,
    Matt Guibord
  • 0 in reply to Matt Guibord
    Prodigy 250 points
    Hi Matt,

    Thank you for the reply. I am sorry that I didn't know you were still looking into my case.

    The clock signal runs constantly but the frequency may change slightly. The maximum period deviation is +/-1% from the ideal period. Is the clock need to be a square wave or it can tolerate mark-space ratio other than 50:50? Thanks.

    Bo
  • 0 in reply to Bo Dong26
    TI__Genius 17340 points
    Hi Bo,

    Thanks for the additional info. I have a feeling this is okay, but still trying to check with design. If the clock is slowly drifting +/- 1% from nominal, I don't expect any issues. There is a duty cycle correction in the part, however I'm not sure if there is a settling time associated with it. Likely duty cycles other than 50/50 are okay, as shown in the datasheet under the "input clock duty cycle" spec.

    Regards,
    Matt Guibord
  • 0 in reply to Matt Guibord
    Intellectual 330 points

    Hi Matt,

    I am working on something similar, and I was wondering what will happen if the condition of the input clock is even worse, say, it lasts for some cycles and disappear for a short period of time. Or the period changes by 10% from one cycle to the one follows (so it is not a slow drift but a sudden change. What can I expect from this irregular clock? Thanks a lot.

    Lingmei

  • 0 in reply to Lingmei Ma
    TI__Genius 17340 points
    Hi Lingmei,

    If the clock disappears then the results will be not be very good. A sudden change is also not good, especially a large change. There is a DLL in the device that is used to set the clock phases throughout the digital block. Jumps in frequency may result in timing errors and irregular outputs. I'll try to find some devices that could work and report back.

    Regards,
    Matt Guibord