Hi all, my ADS58C48 probably is not setup correctly, and the output data from CH-A to CH-D looks weird. Hope somebody here can do a favor. Many thank in advance.
I believe my ADS58C48EVM has been rerouted correctly to a Xilinx ML605 via the TI adapter "FMC-ADC-ADAPTER", because all ADS58C48 serial registers can be read/written correctly from my host PC, where R54/R68/R70/R56 were removed and R55/R64/R71/R104 were connected so that the serial pins were programmable from the FPGA (or from the PC). Here are two examples that I can tell these serial registers are controlled correctly. 1. When BITS 7-6 of register 0x41 are in default model "00", CLKOUTP and CLKOUTM from ADS58C48 output a pair of 20MHz differential clock (input clock 20MHz), but only CLKOUTP has 20MHz and CLKOUTM is 'low' where these two bits are set to "01", "10", "or "11". 2. When BIT 1 of register 0x00 is reset, all registers are reset correctly.
Now the strange thing is that neither "test pattern" nor normal operation outputs correct data from data pins of CHA[0-11], CHB[0-11], CHC[0-11], and CHD[0-11]. I connect an analog 0-1.5V DC signal from a function generator to the analog inputs of AIN_A (J4) to AIN_D(J9). In LVDS mode, the digital outputs are mostly in the pattern of 101010101010, or 100110011001 no matter how the input voltage is changed. In CMOS mode, the digital outputs are mostly in 000000000010, 000000000100, or 000000000000, and occasionally in 111111111110.
I'm more than appreciative if experts here can point out what wrong is in my testing.
Q. Yang
University of Rochester
