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ADS1675 - Bad performance, lots of noise in the time domain

Jeremy Partain1
Prodigy 130 points
Other Parts Discussed in Thread: ADS1675, CDC208, CDC329A

I have an 8 channel ads1675 board connected to an fpga.  I am getting poor performance out of the chips and I think some of it might be related to the CLK input.  I'm running all chips in low speed mode and was able to vary the clock speed via a programmable PLL (CS2300 from Cirrus then running that to an OR gate SN74ACT32N to convert it to a 5v level).  When I get the sample rate of the converter above 800kHz, the noise goes to well below 18 bits. 

The converter seems to be VERY sensitive to clock jitter.  The CS2300 has very little according to the data sheet, so I think the noise may be coming from my board layout.  I have a common clock trace with a via at each A/D converter.  When I put a capacitor on the clock trace I can get the noise down to about 18 bits, but it varies drastically, sometimes its 21 bits, sometimes it is 16. 


Do you have any suggestions?  I'm thinking about designing a new rev of the board using the CS2300 and the CDC208 clock IC.  Do you think this would be a good way to convert from a 3.3v to a 5v clock?

It says in the ADS1675 datasheet that the CLK line needs to be 5v and have a 1ns rise/fall time? 

"For best performance, the CLK duty cycle should be very close to 50%. The rise and fall times of the clock should be less than 1ns and clock amplitude should be equal to AVDD"

Is this even possible at 32 mhz?  All of the clock signals I've ever seen are a triangle wave at best when you get above a few megahertz and dont come close to reaching the power supply rails.  Do you have a chip recommendation?  I've looked heavily at the reference design since we have been having trouble with the noise level on our board and it doesnt look like there is any way the reference design meets the 1ns rise and fall times either. 

  • 0
    TI__Mastermind 23235 points

    Hello Jeremy -

    On the ADS1675REF board, there is a OR gate that is located between the FPGA clock output and the ADS1675.  This gate serves for voltage translation and drive capabilities to achieve the higher speed performance.

    We don't have any experience with the CS2300, but your proposed solution seems reasonable.  You may want to allow a couple different options for prototype testing to ultimately determine the best results for you.

    We can also try and involve some of our clock folks to see if they have any suggestions.

  • 0 in reply to Greg Hupp
    Prodigy 130 points

    Yes sir, I've installed an OR gate on my board for prototyping and its helped alot, but I still get about 18 bits of resolution in the frequency domain. Does this seem reasonable for this chip? I really expected around 20 to 21 bits.

    If you dont mind asking your clock folks what they suggest I would appreciate it.  The 1ns rise/fall time in the datasheet seems really hard to meet with any clock generator I've seen.    Please feel free to make suggestions about what clock to use.


    Also, do you know what the noise floor is on the demo board?

  • 0 in reply to Greg Hupp
    Prodigy 130 points
    I'd really appreciate any help on finding an appropriate way to distribute the clock signal to all 8 of the chips so I can use them for simultaneous acquisitions. Have you heard of any ways to generate a 1ns rise time with CMOS/TLL logic?
  • 0 in reply to Jeremy Partain1
    TI__Mastermind 23235 points

    Hello Jeremy -

    You can reference Table 1 in the datasheet that shows some different ENOB and other performance numbers for different modes of the ADC.

    We will let you know what we can find out from the clock division.

  • 0
    Prodigy 100 points
    Hi Jeremy,
    Getting higher and higher performance out of ADC requires a lot of attention to every detail. Since you don't specify many details of the project, layout, power supplies, etc. it is very difficult to comment. How are you measuring your noise (i.e. are the inputs shorted, what type of front end are you using to drive the converter, what filtering, what bandwidth, how good is your reference, what type of power supplies, etc.). All of those are going to be critical to get over 18 bits. From the table Greg mentioned, as you get to 1 MSPS the noise free bits are down to 16.24, and ENOB is at 18.97, so it doesn't seem that you are miles out from the performance of the chip.

    Some good rules of thumb when synchronizing multiple converters are to make sure that you have a very high quality clock and clock driver for distribution, every device should have it's own dedicated driver (multiple low skew, low jitter driver) and be properly terminated for possible reflections (easiest way is a resistor at the output of the driver, and then possibly a cap or space for a cap and/or resistor at the input clk pin of the converter). It does you no good to have a great clock and then have it degraded by a poor clock distribution driver. Each line to each converter should be an identical length so you can make sure the edges arrive at the same instant on every device. The clocking circuitry should be independent from the digital logic and be considered as an analog source, so dedicated planes, and area of the board away from noisy digital logic, and separate from the analog as well as best as you can. Buffering the digital outputs to separate the digital logic outputs on the ADC from the digital inputs to the FPGA might be an option as well. Shielding around the board, as at 800kHz you can pick up a ton of EMI from lights and computers sitting on your workbench, etc.

    Always remember too that as you increase the output data rate you are increasing the bandwidth and thus allowing more noise into the system so it tends to get noisier. You mention that your noise level varies drastically, this points to an issue to be worked out, it would be better to have a consistent noise level so I would focus on that first, and try to focus on a specific data rate as a worst case (the highest rate that you require) once you hammer that down then you can decrease the data rate, and you should be able to get more bits out of your system (provided the details mentioned above are taken care of correctly).

    My own feeling is that once you go beyond 16 bits, it is very difficult to get direct answers to problems such as yours, it's going to come down to investing the time and research, and applying all of the tips and tricks that the gurus have put out there. Each company provides and enormous amount so search the sites.

    If you can post some more details, and image of layout etc. it might be a bit easier to help out instead of all these general comments.
    Good luck,
    Jason
  • 0 in reply to Jeremy Partain1
    TI__Mastermind 23235 points

    Hi Jeremy -

    So I ran your question by some of our clock folks with the following result based on information in this post:

    Depending on the cap load of the CLK input and PCB trace, you'll need a clock driver that has high output drive capability to achieve 5V swing with 1 ns rise/fall time (or 4 V/ns slew rate). To achieve this slew rate and assuming 5 pF load, you would need a CMOS driver that can support around 20 mA output current and supports the required frequency of operation. Most 5V CMOS clock drivers are older devices. You may consider CDC329A, CDC204, or CDC208.


    Hopefully this helps out a little or points you in the right direction.  Let us know if there are any further questions that we can help with.

  • 0 in reply to Greg Hupp
    Prodigy 130 points
    Greg,

    I was testing the CDC208 as a matter of fact and with it hooked up directly to the oscope (it has 250 Mhz probes), I see a triangle wave at 32 mhz. As for the data sheet, It says Tpzl and Tpzh is anywhere from 4.4 to 12 ns which makes since to see the triangle waveform. How can that chip get a 1ns rise/fall time? The cdc329A does have a roughly 1ns Tr and Tf though so I may end up using that in my final design.

    Jason,

    As for the other info, our reverence voltages are supplied by an REF5025 output through an amplifier with an extremely low pass filter built in. It appears very stable on the scope.

    We measure noise using a 2.9 Hz bin size in an FFT taken at the 750kHz sample rate. The noise floor is around .00008 V to .0001V on a 20 volt full scale input.

    I've reviewed our layout again and definitely found a few flaws with the way the analog traces are routed. I'm going to fix those with our next rev of board. Specifically, the single ended to differential amplifier feeding the ADC does not have a low pass filter built into it and it appears to be getting noise from the main CLK line only on the differential outputs. The input to the amp is very clean. I think this is going to be the source of the noise. When I disconnected the differential amplifier from one of the ADC channels, the noise when down to microvolt levels. I'm fairly certain we have some work to do with the amp feeding the ADC.

    One more question Jason, What values for capacitance have you seen for a clock driver termination cap at the ADC? I'm just looking for a ballpark number, I know mine next board will have to be tuned.



    Thanks for the help everyone.
  • 0 in reply to Jeremy Partain1
    Prodigy 100 points
    The caps are basically just to control the overshoot or undershoot on the edges of the clock. I've seen up to 50 pF for some applications, but if your layout is good and the clock traces are all nice impedances, with series resistors (30 to 50 Ohms) at the output of each driver, you can probably live without them.
  • 0 in reply to Jeremy Partain1
    Prodigy 100 points

    Sorry, have been away for a while. Cap values are just in the low pF area, and are only to provide as mentioned some control over the overshoot, etc. Also helps in filtering any higher frequency noise that may be coupling into the clkin pin of the ADC. The clkin pin should be considered as carefully as the analog inputs.