Hello team,
Samsung has a question on the output phasing on the ADC08d1020. I looked through the datasheet as well as other E2E posts and couldn’t find an answer to the question so I am posting it on the forum.
Their question:
“ I’m using the ADC08d1020, and I’m wondering if you have seen an issue with the output data busses being out of phase? When I have the test pattern generator on, I can clock in the data (in non-multiplexed mode) perfectly. When I take the part out of test pattern mode, the FPGA clocks the DDR data from the I differently from the Q, by one clock cycle. I just wanted to make sure I’m not going up against a known issue. “
Thanks,
Matt