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ADC08D1020 Output Data Phasing

Other Parts Discussed in Thread: ADC08D1020

Hello team,

Samsung has a question on the output phasing on the ADC08d1020. I looked through the datasheet as well as other E2E posts and couldn’t find an answer to the question so I am posting it on the forum.

Their question:

“ I’m using the ADC08d1020, and I’m wondering if you have seen an issue with the output data busses being out of phase? When I have the test pattern generator on, I can clock in the data (in non-multiplexed mode) perfectly. When I take the part out of test pattern mode, the FPGA clocks the DDR data from the I differently from the Q, by one clock cycle. I just wanted to make sure I’m not going up against a known issue. “

Thanks,

Matt

  • Hello Matthew,
    One thing to keep in mind is that in test pattern mode, a pattern is loaded into the device that does not encompass any external delays that may be present. I would first have them check at a lower clock frequency to see if this issue still occurs. I would also check with DDR clock phase of 0deg and 90deg to see if there are any setup and hold issues. This can be accomplished through reg 1h, bit 11. If both of these changes still exhibit the issue, I would turn my attention towards any analog delays that may be present. If there is a consistent 1 clock cycle mismatch, you could simply adjust the FPGA code to shift the data by one clock cycle.