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how to perform the calibration of ADC12D1800

Other Parts Discussed in Thread: ADC12D1800

Hello :

   I am using a ADC12D1800 with the Xilinx K7 fpga. Now I am using 800M Hz sample rate, and the single is 70Mhz sine wave from singal generator. I test the ENOB is olny 6.9, and SNR is 42~44db. The test results did not perform a manual calibration. I read the TI technial document , that calibration can improve the ENOB. But how to perform a manual calibration. Is there more detailed description or a reference design.

  I use the FPGA to pull up CAL pin for 3840 sample clocks after power up, But there is no effect , I doubt that I did not correctly calibrated the ADC12D1800.

  • Hello Listenjhon,
    Please see page 52 of the ADC12D1800 datasheet. It discusses the exact method and length for a calibration. Note there are two ways to perform the calibration, either through SPI (0h, bit 15) or by the CAL pin (pin D6). Both methods are logically or'd together so it doesn't matter which method you choose.
    Regards,
    Luke LaPointe
    High Speed Data Converters
  • hello Luke LaPointe:
    Thanks for your reply. I have already did as the datasheet page 52 said. I pull down the CAL pin for 20ms , and then pull up it for 5us , and then pull down. That meets the requirement of datasheet. But after I pull down the CAL pin , the CALRUN pin became low immediately. I think that Calibration does not work correctly.
  • Hello Listenjhon,

    Does CALRUN ever go high? It should go high after about 1.6us of holding the CAL pin high. If it is not going high, please verify that the CAL bit (Addr: Eh; Bit: 15) is set to 0. If it set to 1, then the calibration will not occur because the CAL pin and the CAL bit are logically OR'd together.

    The correct procedure for calibrating with the CAL pin is as follows:

    Step1) Ensure that the CAL bit (Addr: Eh; Bit: 15) is set to 0.

    Step2) Hold CAL pin low for a minimum of tCAL_L clock cycles (1280 clock cycles / 800MHz = 1.6us).

    Step3) Hold CAL pin high for a minimum of tCAL_H clock cycles (1280 clock cycles / 800MHz = 1.6us). At this point CALRUN will become logic-high.

    Step4) Wait for tCAL clock cycles (5.2*10^7 / 800MHz = 65ms) for calibration to be complete. After calibration is complete CALRUN will become logic-low.

    Step5) Wait an additional 60 clock cycles (60/800MHz = 75ns) before valid data is present at the output.

    Figure 4-8 on page 35 of the ADC12D1800 datasheet shows both the power-on calibration and on-command calibration timing diagrams.

    One other thing I want to quickly verify is the VCMO pin. If you are using AC coupled inputs then it must be tied to ground. Leaving this pin floating can also result in degradation of performance even if the calibration is performed correctly.

    Regards,
    Luke LaPointe
    High Speed Data Converters