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AMC7812 ADC questions

Henry Jung
Prodigy 220 points
Other Parts Discussed in Thread: AMC7812

DEAR. ALL

Could help me 

At the point of DAV_B=0 what recognized red column, does it take 1 usec for LOW of DAV_B pin?

How does ADC work out at the point of Read command case? or at the point of command registration which can read ADCn_data_register just ahead of DAV_B = 0?

  • 0
    TI__Genius 11750 points

    Howdy Henry,

    I'm assuming the above question is directed towards 'auto' mode, as in 'direct' mode the DAV pin stays active low until the ADC Data Register is read.  In auto mode, a pulse of 1us (low) appears on the DAV pin to signify that new data is available.

    In the above ADC Conversion sequence the DAV pin doesn't assert low until all active channels are converted.  The DAV pin asserts low when the last channel is converted, this can be seen in the image you posted above in the "Is this the Last Conversion?".  If it is the last channel being converted the part issues the 1us DAV pulse, then repeats the conversion sequence.

    Once the DAV is read as 'low' the user can then readback the ADC Data Register for any enabled ADC channel.

    Please let me know if this answers your questions.

    Best Regards,

    Matt

  • 0 in reply to Matthew Sauceda
    Prodigy 220 points
    Hi MATT

    “in auto mode, before DAV pin asserts low ( before the last channel is not converted ), if the host processor reads ABD-n-Data Register, how the register value to will be taken?”

    Questions about your answer
    Is there any error issues when DAV prior to LOW version recognizes ADC-n-DATA REGISTER several times with placed AUTO MODE?

    Other questions
    Heard that Channel can undergo influences owing to Conversion data rate with placed AUTO MODE, do you have any idea how to set up Conversion rate?
    Please let us share the details of Conversion rate.

    Best Regards,
  • 0 in reply to Henry Jung
    TI__Genius 11750 points

    Hello Henry,

    The ADC Register structure follows a Double-Buffered ADC Structure.  This is displayed in the image below, but also in page 31 of the AMC7812 DS.  As you can see in the image below the ADC channels have two output buffer registers, one is a temporary register and the other is the Data Register.

    When in 'auto' mode, when the conversion of an individual channel is completed, the data is immediately transferred into the corresponding ADC-n temporary register.  Only after the last channel conversion completes that all data in the ADC-n TMPRY Registers are simultaneously transferred into the corresponding ADC-n-Data Register.  All ADC-n-Data Registers are not updated until this data transfer is complete.  After the registers are successfully latched a 1us DAV pulse is sent to signify that new data is available for read.

    If a read operation is performed before the ADC-n-Data Registers update the user will read ADC-n-Data results from the previous conversion, not from the current conversion.

    To increase or decrease the conversion rate set the CONV-RATE-1 and CONV-RATE-0 bits of register 4Dh.  This information is located on page 67 of the DS, as well as Table 18 of the DS.

    Best Regards,

    Matt