ADS8881 / td-CNV-DO Enable time

Hello Asaka-san,

(a) is correct assuming the BUSY indicator is not being used. If the BUSY indicator is used then 19 SCLK cycles will be required to clock the data out (see figure 53) and the minimum SCLK frequency requirement will increase accordingly.

Best Regards,
Harsha

Hello Asaka-san,

Although option a) is correct as stated in the previous post and 66.67MHz can be used as SCLK, we recommend 70MHz SCLK to easily keep CONVST_HIGH for more than tconv_min for non-busy indicator mode using integer clock multipliers as follows:

70MHz Interface Clock (14.29-ns Time-Resolution)
		Clock Multiplier	Timel (ns)	Margin (ns)
CONVST_HIGH to stay in no-busy indicator mode		50	14.29ns*50 = 714.5ns	714.5ns-710ns = 4.5ns
Data-read		18	14.29ns*18 = 257.2ns
t_quiet		2	14.29ns*2 = 28.6ns	28.6-20ns =8.6ns
	Period (ns)		1000ns
	MAX Rate (KSPS)		1MSPS

With 66.67MHz SCLK and integer clock multipliers for CONVST_HIGH for no-busy indicator mode, the maximum sampling rate is as follows:

66.67MHz Interface Clock (15-ns Time-Resolution)
		Clock Multiplier	Time (ns)	Margin (ns)
CONVST_HIGH to stay in no-busy indicator mode		48	15ns*48 = 720ns	720ns -710ns =10ns
Data-read		18	15ns*18 = 270ns
t_quiet		2	15ns*2 = 30ns	30ns -20ns =10ns
	Period (ns)		1020ns
	MAX Rate (KSPS)		980.4KSPS

Therefore, if 66.67MHz SCLK is finally implemented in the application and 1MSPS is the desired sampling rate, CONVST must be controlled with a high resolution timer so that its HIGH time is exactly 710ns and LOW time is exactly 290ns to avoid entering in busy-indicator mode or violate t_quiet timing.

Regards,

Rafael