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How to use 2x ADCJ4000EVM boards

John McDonald
Prodigy 140 points
Other Parts Discussed in Thread: ADC12J4000EVM, LMK04828

I have two ADC12J4000EVM boards and would like to use an external 3.4Ghz clk and SYSREF to synchronize the two boards.

Both boards will use the 3.4Ghz as the sampling clock. The ADCs are configured in bypass mode with L8, F8, K4.

I would like to use the LMK04828 and was wondering if there is a recommended configuration for changing one or both of the boards?

Thanks,

John

  • 0
    TI__Genius 13335 points
    Hello John,
    I would recommend changing the boards to external clocking as outline on page 22 of the ADC12J4000EVM user's guide. Then you can feed in a synchronous 3.4GHz clock to DEVCLK (and synchronous 1.7GHz clock to LMKCLK). This will allow both ADCs to be synchronized to the same reference clock using the LMK04828.
    Regards,
    Luke LaPointe
    High Speed Data Converters
  • 0 in reply to Luke LaPointe
    Prodigy 140 points
    Luke,

    For test purposes, I enabled the 100Mhz osc out of one board into the other. Both boards wre phase aligned with the 100Mhz.
    I have both lmk04828 programmed to Ext_VCO and Continuous SYSREF. I'm not sure what the best way to have the FPGA synchronize the two sysref outputs.

    How would you program the LMK04828 on the two different boards for the fpga to adjust one of them to align to the primary sysref?

    Or should I use the Sync function to start the sysref dividers. I'm not sure the Sync Pulse traces or SYSREF traces from/to the fpga to each LMK are matched from the FMC connectors to the FPGA on the Xilinx VC707eval board.

    Can the LMK04828 act as a pll and lock the incoming sysref by adding delay to the output sysref without manually setting the delays?
    Or does LMK sync circuit just act as a delay incrementer each time a sync is active?

    Yep, I'm confused.

    Thanks again,
    John