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ADS1232 DRDY always high

Dirk Handzic
Prodigy 205 points
Other Parts Discussed in Thread: ADS1232

Hi,

I am using a ADS1232 with internal oscillator (XTAL1 to GND by 47k). DVDD and \PWDN tied to 3.3V, TEMP tied to GND. AVDD, REFP tied to +5V.

The problem is that the \DRDY pin is always high even though SCLK is low.

I have even tried to send 24 CLK pulses at power up, but \DRDY is stuck at high level???

Regards

Dirk

P.S. SPD, G0,G1,A0 are all low to start with.D.S

  • 0
    TI__Guru** 113765 points

    Hi Dirk,

    Make sure that the AGND and DGND are tied together. Second, make sure that you follow the Power-Up Timing Sequence as shown in Figure 39 of the datasheet. The PDWN pin should not come up high until at least 10us after the AVDD and DVDD supplies are stable.  One delay method is a discrete delay circuit shown in Figure 40.  An alternative method is to connect the PDWN pin to a GPIO pin on the micro and use the appropriate delay.  If you use the GPIO option I would add a pull-down resistor to the PDWN pin similar to the oscillator pin to hold the pin low on power up as many micros will default to GPIO as either tri-state or input.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Prodigy 205 points

    Hi Bob,

    I have modified the circuit now and put a RC delay circuit to \PDWN rather than connecting it directly to DVDD. This has been definetly been part of the problem. Now I can see \DRDY going low  when I send SCLK pulses. However with SCLK low all the time \DRDY is still high all the time?

    Kind regards

    Dirk

  • 0 in reply to Dirk Handzic
    TI__Guru** 113765 points

    Hi Dirk,

    I'm suspecting that AVDD and DVDD are not powering up at the same rate or you may have some connection issue.  In the power up sequence DVDD is used in the RC delay circuit, but both AVDD and DVDD must be fully up before you start the 10us delay.  To see if this may be an issue, you may want to try and use the DVDD voltage for AVDD to see if the correct operation takes place.  You could also make the initial delay longer.  If you used the values in the datasheet, device tolerance may keep you from getting the full 10us delay.  Try increasing the R and/or C values.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Prodigy 205 points

    Hi Bob,

    I have inreased the RC and now it is working. RC was however not the only problem ;) I use the processors SPI in receive only mode and this means I have to disable SPI once I do not want any further clock signals. That tri-stated the CLK pin and everytime I measured it was low (due to the oscilloscope probe). I have now enabled a weak pull-down for this pin and everything works fine now.

    Regards

    Dirk