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ADS5401 high-performance mode

David Sweigart
Prodigy 130 points
Other Parts Discussed in Thread: ADS5401, ADS5474

I'm observing strange behavior when using an ADS5401 with and without the "high-performance mode" enabled.  My setup: I have an AC-coupled, differential input (with no bandwidth filtering) to an ADS5401, and I read out the differential, 12-bit (plus an over-range bit) samples via a Xilinx® 7 Series FPGA.  The CLKIN digitization frequency is 750 MHz.  For all of my tests, I performed the recommended device initialization sequence (see page 27 of the data sheet) which enables the offset and gain auto-correction loop.  The behavior of the ADS5401 output for my two test cases are:

  1. Noise: With no input to the chip, I characterized the noise level for the high-performance mode enabled and disabled.  I found that enabling the high-performance mode increased the ADS5401 noise level slightly.  This led me to believe that the high-performance mode should be disabled for a more noise-free output, but I observed the opposite when inputting real signals.
  2. Input signals: I inputted a very clean, differential 10 MHz Rubidium clock (sine wave) via a Stanford Research Systems FS725.  When high-performance mode was disabled, the output data format was in offset binary even though I set the appropriate ADS5401 register to two's complement.  Is this expected?  I also observed a jagged-looking, digitized waveform with some samples flagged as over-range.  When high-performance mode was enabled, the output data format was in two's complement as expected.  The resulting digitized waveform was also very clean compared to without HP mode, and no samples were flagged as over-range.

Is this ADS5401 behavior to be expected?  In either case, I need to know what this "high-performance mode" is doing.  In particular, I must know whether it has an input-signal or input-clock frequency dependence with regard to the digitized waveform.  I'm currently evaluating this chip to use for a precision measurement where frequency-dependent effects are important.  The ADS5401 data sheet (SLAS946A - APRIL 2013 - REVISED JANUARY 2014) doesn't provide any information on high-performance mode beyond that it's required for "optimum performance" (page 32).  Also note that I've attached a PDF documenting my observations and results along with a table of the ADS5401 register values used.  Thanks for any advice on this topic and help understanding this high-performance mode.

ADS5401_high-performace_mode_results.pdf

  • 0
    TI__Mastermind 29220 points

    Hi,

    The HP1 bit is normally not something that should be touched.  It doesn't do any harm to clear it to zero but the output data is no longer meanigful.  The name High Performance is really not an appropriate name for the bit either.  I did a search for 'performance' in the datasheet and there is one place where that name is used in relation to this bit and I think that should be edited when we next revise the data sheet. 

    The ADS5401 is what we call a pipelined data converter, where the conversion is done by successive pipeline stages of flash ADC.  This data sheet doesn't give a glimpse into the internal structure but if you were to take a look at the front page block diagram of a datasheet such as the older ADS5474 you could see the pipeline structure made more explicit.   Clearing the HP1 bit turns off the arithmetic logic that reconciles the bits from all the pipeline stages letting us look at individual stages.  Not useful at all in normal practice.  Normally we would not make such a bit visible in the datasheet except that in this device you have to turn off this bit in order to use the test pattern registers.  if you try to set the test pattern registers then you don't want this bit to do stuff to your test pattern.  But in all other use cases than the test patterns you need to leave HP1 set for proper operation. 

    Regards,

    Richard P.