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ADS1672 Aliasing frequency for low latency path

Denis Molaro
Prodigy 80 points
Other Parts Discussed in Thread: ADS1672

In table 5 of the ADS1672's data sheet it is noted that for frequency bigger than Fdata/2 there is aliasing, but this does have no sense for me: since I m using a sigma delta I though the aliasing will come over the clock/2 frequency, so 10Mhz in my case. If I have to use a filter that cuts all the bandwidth at Fdata/2 I will lose all the advantages in useing this ADC.

  • 0
    TI__Mastermind 23235 points
    Hello Denis -
    Your comments about aliasing as related to Fdr/2 are correct. However for this device, in Low-Latency Single-cycle settling configuration, the device works a little different than might be apparent. In order to achieve the single-cycle settling, the internal datarate is approximately 2x the perceived data rate. This means the converter is actually outputting on every other datapoint to allow the filter to settle and achieve your desired frequency. So since the actual datarate is 2x expected, then Fdr/2 is roughly the desired/expected datarate, which is what Table 5 is showing.
    If you are worried about aliasing, we would recommend the Fast Response mode of the ADC as show in Table 6.

    Hopefully, this explanation clears up any confusion and explains the behavior. If you still are unclear, please let us know and we'll try and clarify the behavior.
  • 0 in reply to Greg Hupp
    Prodigy 80 points

    Thanks Greg,

    could you give me some advice on how to make the anti-aliasing filter for the two operation modes: single-cycle setting  and fast-response? Which cut-off frequency and rolloff should I use in the two cases if the bandwidth of interest of my signal is 100kHz?

    Denis