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ADS1298 Cascaded Configuration Master/Slave Clocking?

Adam Garrison1
Intellectual 580 points
Other Parts Discussed in Thread: ADS1298

I am designing two ADS1298 chips in cascaded configuration.  Is it a requirement that the CLK should be externally generated when using two ADS1298 chips in a cascaded configuration Currently, we’re feeding the internal clock of the master ADS1298 chip into the slave ADS1298. Is this a valid topology?

Regards,

Adam

  • 0
    TI__Mastermind 38745 points

    Adam,

    There is no requirement for an separate master clock using the ADS1298 in cascaded format. The topology you have chosen with the internal clock of the master device being used as the external clock for the slave device is definitely valid. Just remember to have the CLKSEL pin on the master device held high and the CLKSEL pin of the slave device held low. You must also configure the clock configuration settings appropriately in each of the respective device registers. For more information regarding daisy-chaining of devices, refer to page 59 of the ADS1298 datasheet. If you have any followup questions, please do not hesitate to ask.

    Regards,

    Brian