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ADS8688 - tHT_CKDO

Other Parts Discussed in Thread: ADS8688

Hi all,

Would you mind if we ask ADS8688?

<Question>
Our customer will use SPI(master side) which the data holding time  is 40ns min.
ADS8688's tHT_CKDO is min 10ns. 
Master side 40ns > ADS8688's tHT_CKDO 10ns, so is it enough time to hold time, isn't it?
It means that if  the data hold time is over 10ns, the hold time is enough to get the SDO data from ADS8688.
Is our recognition correct?

Kind regards,

Hirotaka Matsumoto 

  • Hello Hirotaka San,
    The tHT-CKDO spec specifies the time for which the previous SDO data will be valid.
    SDO is output from ADS8688 & hence the timing for this signal is controlled by ADS8688 device with respect to SCLK.
    When the ADS8688 is driving SDO pin, the SDO data will change after falling edge of SCLK pin. This change can happen anywhere after 10nesc from the SCLK falling edge. The master side should read before 10nsec from the SCLK falling edge to read the correct value.
    Thanks & Regards,Shridhar.
  • Shridhar san,

    Thank you for your reply!
    In our customer case, so the tH(input data hold time) spec of Master side is 40ns, the master side doesn't read with falling edges of SCLK correctly.

    So inorder to read the SDO data from ADS8688,  the tH(input data hold time) spec of Master side is required less that 10ns, right?
    Or, usually, should Master side read datas from ADS8688 with rising edges? 

    Is our recognition correct?

    Kind regards,

    Hirotaka Matsumoto

  • Hello Hirotaka san,
    The data needs to be read by the master on SCLK falling edge & the hold time should be less than 10nsec.
    Anythime after 10nsec from SCLK falling edge, the device will drive new SDO value.
    Page 33 of the datasheet explains the SCLK edge related events in detail.
    Thanks & Regards,Shridhar.
  • Shiridhar san,

    Thank you for your reply.
    Ok, we got that our customer's CPU(data hold time=40ns) can not read SDO data from ADS8688.

    Kind regards,

    Hirotaka Matsumoto