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INTERFACING DAC5674 with XILINX SPARTAN 6 SERIES FPGA

Mohit Hada
Intellectual 745 points
Other Parts Discussed in Thread: DAC5674

Hi,

We have very successfully used DAC5674@ 200MHz with ACTEL FPGAs having LVPECL outputs as for CLK and CLKC inputs of DAC5674.

But now we want to switch to XILINX FPGAs - SPARTAN6 SERIES which does not have LVPECL output buffer.

I request to please explain how can the LVPECL clock inputs of DAC5674 be interfaced with LVDS outputs of FPGA. What is the exact circuit for doing it?

Below are two docs which say some about this but they confuse me further.

INTERFACING LVDS AND LVPECL 1.pdf

  • 0
    TI__Genius 12965 points

    Hi Mohit,

    If you look at page 2 and 3 of your attached document and the figure 5 you can see how the LVDS to LVPECL interface can be implemented.  The DAC5674 data sheet outlines the recommended PECL interface on figure 32 - using this along with the app note you posted you can figure out the correct interface.

    As the app note states, the key will be to solve the equations for figure 5 to meet the termination and common mode voltage requirements looking from the LVDS side and also from the PECL side - solving these 2 sets of equations will yield the appropriate resistor values.

    Ken.

  • 0 in reply to Ken C
    Intellectual 745 points

    Dear Ken,

    The doubt is that there is another application note which says they can interface directly without any such termination resistors apart from a 100ohm differential matching resistor and so I am confused.

    I have attached the application note. Requested to please check page 6 of this application note.

    Thanks and Regards.LVDS_LVPECL2.pdf

  • 0 in reply to Mohit Hada
    TI__Genius 12965 points
    Hi Mohit,

    We will look into this and get back with you. The concern is whether there is enough margin on the differential level of the LVDS lines from the FPGA to trigger our PECL CLK input circuit.

    Ken.
  • 0 in reply to Ken C
    Intellectual 745 points

    Hi Ken,

    Thanks i will wait for your reply. However, this is what one of the xilinx representative had to comment on my same query.

    Response Start:-

    I looking though the data sheet for the DAC5674, and while I can see several circuit diagrams suggesting how to drive the clock inputs, I can't find any DC specifications for them.  Specifically, what is the minimum differential voltage swing required for the clock.  With a cap-coupled clock and the part having internal biasing resistors on its clock inputs, the common-mode voltage doesn't matter and you just need to be sure that the drivers have enough voltage swing.  Typically the swing on LVDS into 100 ohms is lower than the LVPECL swing in the circuit shown in figure 32.  However if the input requirement is low enough that may not matter.  You can use one of the "MINI_LVDS" standards to get a little more output swing.  At 200 MHz you could also use complementary LVCMOS outputs (driven with two ODDR2 output flops in opposite phase) and a resistor divider that provides you with pretty much whatever swing you need.  If LVDS is good enough (and it's not clear from the TI data sheet, so you may want to ask them why this isn't spec'd), then the circuit would just look like a differential transmission line with 100 ohms across the end and the coupling caps right at the ADC.

    -- Gabor
    Response end.
    I will request you to please sort this at the earliest possible and explain me in the simplest language.
    Regards.
    Mohit

  • 0 in reply to Mohit Hada
    TI__Genius 12965 points
    Hi Mohit,

    The folks at Xilinx are basically saying the same thing - we need to understand the minimum differential voltage level on CLK/CLKC that will trigger the clock circuit. This is not spec'd in the data sheet and will require some discussion with our design team to understand how much margin we have from the standard LVDS differential voltage swing.

    Ken.
  • 0 in reply to Ken C
    Intellectual 745 points
    Hi Ken,

    I will wait for your reply on this.

    Thanks.

    Mohit
  • 0 in reply to Mohit Hada
    TI__Mastermind 20541 points
    Hi Mohit,

    We tested the DAC5674 EVM to figure out minimum differential voltage between CLK and CLKC below which the DAC5674 will no longer be operational. The DAC stopped working below 50mV of differential voltage between CLK and CLKC which is within the requirements for LVDS.

    Since this parameter was only tested on one EVM, some head room should be kept for the process, temp and voltage variations between different parts.

    LVDS should be good enough to drive the CLK AND CLKC.


    Regards,
    Neeraj
    HSDC
  • 0 in reply to Neeraj Gill
    Intellectual 745 points
    Hi Neeraj,

    Thanks for the reply. So can I now safely connect LVDS with -> [100 ohm differential impedance + Coupling caps] @ the DAC clock terminals - CLK and CLKC.

    Kindly confirm.

    Thanks.
  • 0 in reply to Mohit Hada
    TI__Mastermind 20541 points
    Hi Mohit,

    As mentioned in the last post, I think LVDS should be high enough to drive CLK and CLKC of the DAC and you can connect LVDS with -> [100 ohm differential impedance + Coupling caps] @ the DAC clock terminals - CLK and CLKC.
    But TI cannot guarantee anything since we don’t test for these parameters in the datasheet.

    Regards,
    Neeraj
    HSDC
  • 0 in reply to Neeraj Gill
    Intellectual 745 points

    Hi Neeraj,

    Just help me in this. Tell How have you connected the LVDS Interface with DAC clock pins on the EVM. I have not seen the circuit schematic of it.

    Thanks and Regards.

  • 0 in reply to Mohit Hada
    TI__Mastermind 20541 points

    Hi Mohit,

    The picture is from the page 24 of the DAC5674 EVM I edited it just to show the input clock connections.


    I used a Sine wave as an input to the SMA INPUT and measureD the differential voltage between CLK AND CLKC and observed the voltage below which the DAC was no longer operational. This is how the measurement was done.

    Regards

    Neeraj

    HSDC