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ADS1271 SPI Interface SCLK

yang zhou
Prodigy 70 points
Other Parts Discussed in Thread: ADS1271

For ADS1271 SPI interface, is it OK if SCLK and CLK are driven by different clock source? Should SCLK and CLK stay in phase? Or I just read out the data after the DRDY\ goes active no matter what phase or cycle CLK is?

In the spec, it says:"For best performance, limit fSCLK/fCLK to ratios of 1, 1/2, 1/4, 1/8, etc."  So if my CLK is 16MHz, my SCLK should be 16MHz, 8MHz, 4MHz and etc. What if SCLK is something else? Is there any shortcoming if it is say 10MHz?

Thanks!

  • 0
    TI__Mastermind 23235 points
    Hello Yang -
    To answer your first question, yes, SCLK and CLK are very frequently driven from separate clocks, so this is OK. The data out is always read with respect to SCLK and DRDY. The CLK signal is used for the internal clocks of the ADC.
    For your second question, your understanding is correct. We have found the specified ratios of SCLK to CLK provide the best performance results. You can use other ratios (within the timing specs), however you may not see the optimum perfomance.
  • 0 in reply to Greg Hupp
    Prodigy 70 points

    Thanks, Greg.