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For How long is data available on ADS1248 after DRDY pulses

Tomas Larsson1
Prodigy 130 points
Other Parts Discussed in Thread: ADS1248

In our current setup, we keep the START-Pin high, to avoid the converter goes to sleep.

We are using 20 SPS.

We use the RDATA command to retreive data

After the pulse on DRDY-Pin, for how long time is correct data available, Before it's corrupt by a new conversion result.

I would assume that the data buffer at some Point will be updated by new conversion result

The data sheet is very unclear about this.

In our setup we have 5 ADS1248, all of them receives the same channel setup, and we use the SYNC command to sychronize them.

The DRDY pins is then ORed together and routed to an external interrupt-pin on the processor, but currently we are only polling the interrupt flag, not using any interupts on the processor.

  • 0
    TI__Guru* 97455 points
    Tomas,


    I'm sorry that the datasheet is a bit unclear on the readout of the data. Let me explain this through the different configurations of the device.

    Default mode (RDATAC)

    The ADS1248 is in RDATAC mode as a default. This means that the data continuously being placed on the DOUT register every time a new data is available.

    In this mode, you can choose to simply clock out the data with SCLKs without having to send an RDATA command. Note that if the /DRDY goes from high to low, it means that there is new data available and the DOUT register will get updated. This means that if you are doing any data transaction, you must clock out the data before the next /DRDY pulse.

    If you are in RDATAC mode and still use the RDATA command, that is fine too. In that case, the first 8 bits used to clock in the RDATA command will clock out the first 8 bits of data from DOUT (which you would just throw away). Once the device gets the complete RDATA command, it will reload the most recent data onto DOUT and you'll be able to clockout the 24 bits of data. Just as in the first case, you must complete the transaction of reading the data before the next /DRDY or else DOUT will get loaded with new data as soon as it is ready.

    Just like reading data, reading a register should also be done between /DRDY indications. If you're reading a register and then the /DRDY comes along, the DOUT will be updated with the ADC data and forget about reading the registers.

    Stop reading data continuously (SDATAC)

    Using the SDATAC command, it tells the ADC to stop reading data continuously. Note that this does not tell the ADC to stop converting, it simply tells the ADC to stop updating the DOUT register with data (this will occur after the next /DRDY pulse after the command). In this mode, you need to send an RDATA to get the ADC conversion. Since the DOUT register is no longer being updated with each conversion, you can send the RDATA at any time to get the most recent conversion.

    The way you describe your system. It's good that you use the SYNC command to make sure the devices' data output times line up. I would do this every for every data read or the internal oscillators will start to get out of sync.

    Let me know if you have any other questions.


    Joseph Wu
  • 0 in reply to Joseph Wu
    Prodigy 130 points
    So, basically if I understand it correctly, conversion data is dubbebuffered and the new conversion result isn't placed in the readout buffer until the DRDY signal triggers? And subsequently transferred to the SPI shift-register when the RDATA command is received
    So, as long as I don't get a DRDY when I am reading the result, I should be Ok
  • 0 in reply to Tomas Larsson1
    TI__Guru* 97455 points
    Tomas,


    That's correct for the RDATAC mode. You can clock it out with just SCLKs or you can issue the RDATA command and clock it out.

    As long as there aren't any /DRDY indications within the data transaction, the data read should be clean.


    Joseph Wu
  • 0 in reply to Joseph Wu
    Prodigy 130 points
    And for the mode we are running, where we issue the SDATAC in the setup.
  • 0 in reply to Tomas Larsson1
    TI__Guru* 97455 points
    Tomas,


    If you issue the SDATAC, then the DOUT is not automatically updated with data at the completion of the conversion. DOUT will only be updated when you try to read data or when you try to read the registers.

    Note that the SDATAC will take place after the completion of the conversion that is in progress. So there will be one more update after issuing the command at the next /DRDY indication. After the device completes the conversion in progress, it will update the DOUT with the data and then stop future updates.


    Joseph Wu
  • 0 in reply to Joseph Wu
    Prodigy 130 points
    Yes I know that, however that's not my question.
    As I understand it:
    We issue a SDTAC command during setup of the converter.
    We keep START High all the time (as far as I understand it its the only way to avoid sleeping mode and to keep the IDAC 's working continuously).
    We are using the DRDY Pin to monitor the progress.

    The converter is doing continuous conversions at a 20SPS.
    Some time after the conversion Is ready, the output buffer is updated with the new conversion and the DRDY signal is triggered
    Since we are polling the DRDY we do not know exactly when it is happening.
    We issue a RDATA command to transfer the content from the buffer to DOUT, subsequently clocking it out.

    So, when is it unsafe to issue the RDATA command?, I.e. to avoid to do an RDATA in the middle of a buffer update.

    Furthermore is it any other way to keep the IDAC 's running, supplying the IDAC pins even at sleep mode, apart from keeping START high?
    What is the max capacitive load on the IDAC output, we are currently using 100n on the IDAC pin and then 1k in series with the RTD + CMR and DMR filters on the inputs as well as the REF-Inputs.
  • 0 in reply to Tomas Larsson1
    TI__Guru* 97455 points
    Tomas,


    If you are in SDATAC mode, there should be no time unsafe to issue the RDATA command. The command shouldn't interrupt the ADC output or the transfer of the ADC data to the DOUT register.

    As for the second question, the I believe that you should be able to keep the IDAC running as long as the reference is running. In the MUX1 (Multiplexer Control Register 1) register, Bits 6:5 control the reference during this condition.

    If you set these bits to 01, the internal reference is always on, and should keep the IDAC on. If the value is 00, the IDACs won't work, and if the value is 10 or 11, the reference will shut off when a shutdown opcode is issued or when START goes low.

    There shouldn't be a max capacitive load on the IDAC output. The output is a current source output and there isn't any voltage feedback that might cause instability from a capacitive load.


    Joseph Wu