• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 46 subscribers
  • Views 516 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

VSP3210 impulse spikes with very stable amplitude

Alexander Philippovich
Prodigy 20 points

Hi, I am using VSP3210 with Hamamatsu CCD sensor (S8982) . The circuit does not work properly. The circuit assembled on 4 layer PCB with separate DGND and AGND (in one layer) joined at one point under ADC and separated by cutouts,similarly for digital and analog power supply. Analog supply obtained from digital and isolated from digital.

ADCCK  1 Mhz

CK1   rise 300ns after ADCCK rise,  fall 100ns before ADCCK fall

CK2   rise  300 ns after ADCCK fall, fall 100ns before ADCCK rise

ADC used in 1-CCD mode; for signal from CCD used Red channel. Config Reg = 0x88; Red Bias = 0x200;Red Gain = 0x00;

/OE = GND allways; CLP = VCC during unused black pixels; VDRV = +3.3V;

Problem is the next: When I don't connect CCD to my board, and Input signal coupled from DC by 0.1 uF. R = 5.1 kOh  input resistor for emitter follower  for CCD. I see several spikes on my picture (all pixel is a noise near 12 rms). Spikes have constant amplitude max - min codes from ADC (0x4FF(1279) - 0x200 (512)=  0x2FF (767) )  and consist from two pixel  with min code and next with max code. If I change gain to 5 from 0 or change only bias to 0x1FD I see much more spikes on my picture.

I think it may be wrong  ADC convert. What do you suggest me for correct this problem?

  • 0
    TI__Expert 3370 points

    Alexander,

    Could you please

               send the emitter follower portion of the circuit and a sample of the data.

               The register settings being used for teh VSP3210

    Also, could you please try grounding input to the AFE with 0.1uF cap and taking measurements. You should see a small signal with a standard deviation of approx 10 LSB.

    Regards,

    Werner

  • 0 in reply to Werner Metz
    Prodigy 20 points

    Werner,

    Problem are solved. It was error in FPGA code which read hi and low bytes from different ADC words.

    When  ADC output code near 0x01FF,0x0200,0x01FF  FPGA captured 0x02FF and 0x0100 codes. That codes I was see as spikes

    with very stable amplitude.

    Regards,

    Alexander

     

  • 0 in reply to Alexander Philippovich
    TI__Expert 3370 points

    Alexander,

     

    Glad to hear the byte order issue was resolved. Swapping bytes or swapping big-endian/little-endian bit order is not unusual in fpga interfaces to the AFE.

    One practice is to build in a little test counter in the FPGA that can be mux'ed  into the AFE input path in the FPGA.Then increment the counter and read the FPGA data path to verify the bit order and byte order of the data path. The counter can be removed later in the design cycle.

    Also, some TI AFEs have the ability to generate a digital test ramp on the outputs as part of a test mode. This is also useful for verifying bit and byte orders. Unfortunately, the VSP3xxxx devices do not have this capability.

    I iwll mark this thread as answered unless you have further questions on the topic,

    Regards,

    Werner Metz