ADS8688 - SCLK Falling edge to next data valid delay

Hello Hirotaka-san,

The SCLK falling edge to next data valid delay should be <34ns.  If tSCLK min is 59ns, and tSU_DOCK min is 25ns; the SCLK falling edge to next valid delay is 

 59ns-25ns <34ns.

Thank you and Regards,

Luis

Luis san,

Thank you for your reply.

Kind regards,

Hirotaka Matsumoto

Hello Hirotaka-san

Typically the host will read the data from the device in the subsequent falling edge of the SCLK clock signal. The t_{HT_CKDO} (hold time SCLK falling to (previous) data valid) spec in the datasheet is 10nS minimum.   Therefore, the host can read data during the SCLK falling edge. The SDO is updated with a new value >10nS after SCLK falling edge.

-Does the data valid delay time depend on SCLK? The min/max specs are given for temperature range -40C to 125C with SDO load=20pF. The timing specifications are valid provided that the max frequency (17MHz) is not exceeded. The minimum specification limits for t_{HT_CKDO} (Hold time SCLK falling to (previous) data valid on SDO), and the minimum t_{SU_DOCK} (Setup time SDO data valid to SCLK falling) are valid regardless of SCLK frequency.

Could we control the data valid time on SDO to have enough time to acquire data with slow back-end logic? Since the SDO is updated anytime10nS after SCLK falling edge (t_{HT_CKDO}), and since (t_{SU_DOCK}) is a minimum of 24ns; it is possible to read data on subsequent SCLK falling edge.   Also, in applications where SCLK frequency is slow, since SDO is updated with new data sometime 10nS after SCLK falling edge, it may be also possible to read data on SCLK rising edge. What SCLK frequency is used in this application?
What does cause to issue the next data bit; falling edge, rising edge, or etc.? The datasheet shows that the SCLK falling edge triggers the new SDO data. The previous data is held on SDO for 10nS after SCLK falling edge and the SDO updates new data 10nS after SCLK falling edge.

-       Can you provide a detailed description of the problem? Please provide an oscilloscope plot of SPI signals (CS, SDO, SCLK, SDI) while reading conversion data. Please let us know what the expected conversion data is and the actual data that is read on the SDO pin.

-       Please let us know what is the SCLK frequency is used.

Best Regards,

Luis