Hi,
I am investigating a problem which we have using the DAC7716. The problem we see is, that controlling the DAC depends on the capacitive load on the MOSI line. As the signal integrity of all lines is very good (verified with a 6GHz scope and 1Ghz active probes), this indicates very much that the timing of the SPI bus is the problem. The SPI is clocked with 10MHz, so there should be no speed issue.
A slight capacitive load (10pF) on the MOSI line makes the device work. This indicates that the data line needs some additional delay. In order to verify what the device internal SPI registers "see" I observed the MISO output of the DAC. This does reflect the input data shifted by one access (i.e. 24 bits/ 1 chip select cycle) later.
Now here comes the interesting part. The MISO does reflect the input data well with the capacitive load, but is shifted "forward" by one bit without the load. This would indicate that the MOSI line is sampled just around the time where the MOSI line changes. If we delay a little, it gets the right bit, if we don't delay it is one bit early. Now, the datasheet says that the device samples at the falling edge, but I see this behaviour at the rising edge!!!
To sum up, a day's worth of measurements indicate that MOSI is sampled at the rising edge of SPI CLK, not at the falling edge as the datasheet says.
Could that be the case?
There is one additional thing you should know: We don't quite keep the power sequence which is described - we start up with the digital supplys, then with the positive analogue supply, followed by the negative analogue supply (the datasheet says we should start up the negative analogue supply before the positive one). However, I would be surprised if this would influence the devices SPI logic side.
I would appreciate a quick answer!
