One of our customer is using DAC3482/ DAC34H84 in Defense project.We have following queries .
Queries are mentioned below:
1-The tested devices will have updated date code. For the RKD package option, the tested devices will have date code that start 36J or later. For the ZAY package option, the tested devices will have date code that start 3B or later. Refer to Figure 1 for the location of the date code for the respective packages.This is taken from the DAC3482 datasheet page no-17.
Could you let us know how we will take care of these things while ordering this part?
2- DAC3482 datasheet page no-12 mentioned CLKVDD, DACVDD supply is typical 1.29V while running in FDAC Sample Rate ≥ 1GSPS, PLL ON.
Would this condition be valid for FDAC Sample rate <1GSPS?Or do we need to provide the option of 1.2V.
3-If you go to DAC34H84 datasheet page no-13, You would find when PLL is on, Fdac rate can go up to 1000 MSPS. While it's written in general that it can go up to 1.2 GSPS.
Would there be any issue while running FDAC 1.2GSPS while PLL is on?
4- Please provide design support files for DAC3482 & DAC34H84(Schematic & layout).