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Suggestion on simulating ADC08D1520RB FPGA performance

bridget yu
Intellectual 910 points
Other Parts Discussed in Thread: WAVEVISION5

on Virtex-4 it comes with totally more than 110 inputs and outputs. To best simulate it, we need to know all information sequentially sent from DLL to the board.  For example, the data sent from including info communicating between PC and Cypress chip. I wonder is there any FPGA test case example to allow our programmer a sense how to set  proper values to test FPGA image.

Thank yoU!

-Bridget

  • 0
    TI__Mastermind 44680 points

    Hi Bridget

    The detailed documentation you are looking for does not exist and the original developers of the Wavevision system are no longer available. No FPGA simulation test bench exists for this design.

    The FPGA source code is provide to help customers initiate their own development, but that information is provided as-is. The main intention is to provide the details of the data capture interface from the ADC data bus. Our expectation is that customers will be designing the rest of the FPGA features to work with the other aspects of their end system rather than interfacing with the Wavevision 5 evaluation tool.

    Best regards,

    Jim B

     

     

  • 0 in reply to Jim Brinkhurst1
    Intellectual 910 points
    Hi Jim,

    Thank you very much for your reply.

    I feel sorry those developers are not longer available at TI. About the new FPGA design, I try to eventually send data to PC via DLL for visually verification. Basically, I am try to interface with DLL, not WaveVision5.

    Thanks.
    -Bridget