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ADS1278 in modulator output configuration

hans-juergen
Prodigy 65 points
Other Parts Discussed in Thread: ADS1278

Dear All,

we have designed a PCB based on the ADS1278 working in modulator mode. CLK is fed with 8,192 MHz and the low speed mode Mode[1:0] = 11, CLKDIV = 0. The decimation (5th order CIC followed by a 3 stage FIR) is done externally in the DSP. In the attached example the 1,024 MHz input stream is decimated down to 400 Hz and the input signal is 7 Hz-sinus. Unfortunately, we observe heavy harmonics in the FFT that  we cannot explain. The input is driven differentially centered at 2.5V and is very clean. Likewise, the REFIN is very clean, too. Obviously, there is a strong non-linearity geoverning the measurement. This not obvious in the time signal but dominnat in the FFT. Having verified the analog input and the digital processing, I was wondering whether we are oeprating the device out od spec. Does anyone have an idea where this non-linearity in modulator output is coming from?

  • 0
    TI__Guru 66406 points
    Hello Hans,

    Thanks for your question.

    It seems like you are ADS1278 modulator mode correctly. Have you compared your filter output to the ADS1278 filter output? The OSR is fixed to 64 in all modes except High-Resolution Mode. If you can, adjust your filter decimation ratio to 64 for a better comparison.

    If you would like, I can also review the ADS1278 portion of your schematic to make sure you didn't miss any recommended connections.

    Best Regards,
  • 0 in reply to Ryan Andrews
    Prodigy 65 points
    Dear Ryan,
    thank you for your answer. I found that some wrong capacitor values in the analog bessel filter were used. Having fixed this, it looks much better (do not know how to attach the new plot in this reply).

    I am still puzzling what the different modulator modes imply, such as low power and low speed. Both output at fclk/8. Practically, I do not obserbve any difference in the result.

    Best regards
    Hans
  • 0 in reply to hans-juergen
    TI__Guru 66406 points

    Hi Hans, 

    I'm glad that you found the issue.

    We've defined the different modulator modes to provide multiple performance vs. power consumption options. For example, both Low-Power and Low-Speed modes can run the modulator at fCLK/8, but Low-Speed Mode is limited to a master clock of 5.4MHz, which significantly reduces AVDD current to 9mA.

    Best Regards,

  • 0 in reply to Ryan Andrews
    Prodigy 65 points
    Thank you Ryan,
    in our case fclk = 8.192 MHz, so selecting low speed mode would be out of spec, wouldn'i it? As far as my measurments are concerned, I do not see any difference between low speed and low power mode running at 8.192 MHz.