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ADS8363 reference stuck at 3.2v

Bob D.
Expert 2430 points

Other Parts Discussed in Thread: ADS8363, ADS8363EVM

Hi, I'm using an AD8363 with the ICEV2 EVM. When I power my board, the Ref01 output is at 3.2vdc. According to the DS, this signal should be 2.5vdc at power up. I've tried writing data to the device to change the ref01 value, but nothing seems to change the output voltage. I've verified all of my power pins are at the correct voltages (5 analog power and 3.2vdc digital power). M0=0, M1=1. I've also verified all of my SPI signals are per the DS.

 In reading the manual, it appears this output should be no more than 2.5vdc. Any idea why I'm seeing 3.2vdc?

  • 0
    TI__Guru**** 183171 points
    Hi again Bob,
    The default level of the reference on the ADS8363 is 2.5V, but you actually need to write to the RPD bits in the REFDACx registers before you see any voltage on the REFOUT pin. Can you provide a schematic or general description of your connections to the ICEV2 board? Are you using one of the ADS8363EVM boards or is the hardware for the ADS8363 of your own making?
  • 0 in reply to Tom Hendrick
    Expert 2430 points

    Hi and sorry for the double post. E2E was locked up on my system. I found the issue with the 3.2. It was due to my opamps connected to the Ref01 output pin. I now have the pin floating and see 2.5vdc. The problem still is that I can't change the value. Here is what I'm doing:
    1)Write 0x1000 (update control register all)
    2)Write 0x1002 (ref01 write)
    3)Write 0x0 (should update ref01 and set it to 0v)

    My setup is the ICEv2 with my own board plugged in to pick up SPI1_0. I have a CPLD that routes the SPI1_0 signals to the A/D as well as generating the CONVST/RD signal on the first clock to the A/D with CS low. My data out from the ICEV2 is left shifted (MSB of 16 bit word is first bit out of SPI Tx, so the "1' in step 1 is the fourth bit clocked out.) and my word length is set to 20 bits. My SPI is set to clock on falling edges.

    Regarding the RPD bit, it's not clear from the data sheet what this should be set to. On page 23 it states RPD=0 for the output voltage enabled but in figure 40 the diagram shows a "1" and states  RPD = ‘1’ REFDAC1 enabled. Which is it?

  • 0 in reply to Bob D.
    TI__Guru**** 183171 points
    No worries on the double post Bob,
    Are you toggling the RD pin before you send your SPI command? The RD pin also acts like a write when you are configuring the registers. The other thing to note is that RD must see a falling clock edge while it is high. If RD is one clock wide, it should go high and then low on the rising SCLK edges - which makes this challenging if you are using a true SPI port. The register default is 0x7FFF, so to enable the reference you should wrtie 0x1FFF to trun it on at 2.5V. I see what you mean in Figure 40, so I'll see where that typo came from and get it fixed.
  • 0 in reply to Tom Hendrick
    Expert 2430 points

    Hi Tom,

    Can you please check your numbers? The data sheet states the data field is 10 bits and the RPD is 1 bit. 0x7FFF and 0x1FFF have too many bits.

    Here is a screen shot of my signals. Please let me know if you see anything strange. This is writing the 0x1002 for the REF01 write command.

     

  • 0 in reply to Bob D.
    TI__Guru**** 183171 points

    Sorry Bob -

    I added an extra four bits, 0x07FF and 0x01FF is what I meant.  With CH 4 as RD+CONVST you need to ensure there is enough setup and hold time against the falling sclk to satisfy tS1 and tH1 noted on page 11 of the datasheet.  Also, that 'clock' during RD does not count in the SPI transfer - for both input and output data, the MSB would be on the next clock.  If RD is getting acknowledged, the ADS8363 thinks you are writing 0x2004. 

  • 0 in reply to Tom Hendrick
    Expert 2430 points
    HI Tom, So it sounds like I need to set my data width to 21 bits since I'm timing RD/CONVST off of SCLK? I thought I was exactly matching the diagrams in the data sheet. Please see figure 40. It shows 20 clocks with RD/CONVST coincident with the first clock.
  • 0 in reply to Bob D.
    Expert 2430 points

    Hi Tom, So with 21 bits I am able to update the Ref DAC's as expected. I'm assuming you agree that figure 40 in the data sheet is wrong, in that the convst/rd bit should be on the left of the vertical line instead of the right. This error in the document caused me quite a bit of unexpected delay in development.

     One more question, I"m seeing a lot of clock noise on the Ref01 output ever time I write to the device. Is this expected behavior?

    Thanks,

    Bob

  • 0 in reply to Bob D.
    TI__Guru**** 183171 points
    Hi Bob,
    Figure 1 makes the timing relationship of SDI and SDO pretty clear with respect to the RD input. I'll see what can be done to make Figure 40 better, and get that typo with respect to the RPD bit corrected. Regarding the clock noise on Ref01, some noise is common as the conversion process takes place. Each bit is tested against the reference so there is some capacitive switching going on inside the device. The recommended 22uF capacitor on the REFIO should help reduce the noise.
  • 0 in reply to Tom Hendrick
    Expert 2430 points
    OK, thank you.