Hello,
I'm using the ADC128S102QML and have questions about conditioning the inputs as well as possible work-arounds for some of its vulnerabilities.
My first question is about input conditioning. Although a low source impedance is recommended, we have a high source impedance and would like to keep it that way (for isolation and to eliminate extra parts). One solution we've considered is idling the clock to the ADC during the tracking phase so that tracking happens for a longer time. Similarly, we've considered giving the device an extra falling edge of the clock so that it enters tracking mode for the long period between samples (we sample at a rate of 800 us). It seems like the device would tolerate a long tracking period (clock stuck low at clock 1), but can someone at TI verify that this is OK? Some of our ideas depend on what happens to the internal sampling cap, whether it gets depleted after each sample, whether it gets charged somewhere, or whether it retains the previous sample. Can someone explain what happens to the charge on the cap after a conversion please?
Another question we have is about the input protection. We do have some inputs that are driven by op-amps, but those op-amps are powered by rails (+/-5V) that exceed the ADC (4V). During turn on and off (or due to a failure), it's possible the input to the ADC could step out of the absolute maximum ratings. Can the protection diodes handle some current for these times? We assume we can put 1k in series with them (again, raising the source impedance) to limit the current to +/-5 mA below maximum limit, is that safe enough? Do we need external diodes?
Finally, regarding the power sequence requirement that Va be at or above Vd, we will likely violate this unless we change our supplies. Can we get away with using an external Schottky diode from Vd to Va so that the internal one doesn't get turned on? Looks like the spec sheet says the ADC can tolerate 300 mV. We're talking about a short period, hundreds of ms at most.
Thanks for the help,
Robert
