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How to set clkjesd_div in DAC38j84?

Other Parts Discussed in Thread: DAC38J84

I’m using DAC38j84.  Can anyone provide guidance on how to set clkjesd_div in config37(0x25)?  The datasheet doesn’t say if the JESD clock depends on any configuration parameters although it seems likely that the DACCLK, L, M, F, S, and SerDes Gbps will have an impact.  I can’t use the quick start option in the TI DAC GUI to set all the configurations I need.

  • Hi Scott,

    The JESD clock divider can be caluclated by the following equation:

    JESD clock divider = Interpolation * L / M

    I expect that the DAC GUI can generate every configuration that's possible. Note that there are some clocking limitations, which may be the case if the GUI is giving you an error message. If you've found a sequence that is not possible, please let me know. I can help you find the proper configuration.

    Regards,
    Matt Guibord

  • Matt,

    Thank you for the JESD clock divider formula.

    I want the DAC GUI to allow me to select the frequency into the DAC CLK pin and then suggest PLL settings that would work given other settings (like input rate and interpolation) or alarm if the DAC CLK pin frequency is not possible.

    Does the DAC38j84 internal DAC CLK (regardless whether DAC PLL is used) need to be a particular frequency to support any DAC functionality, for example, interpolation?

    Ideally I would like to find a configuration that minimizes power. Lets say I have an application that normally drives DAC CLK at 200MHz, but I can optionally drive the DAC CLK pin on my custom board at 100MHz(using DAC PLL to get to 200MHz internal) or 200MHz(bypassing DAC PLL). If I could just change the SerDes PLL settings to accept 100MHz input AND bypass the DAC PLL that would probably save the most power. This is the line of questioning that I am having trouble answering using the DAC GUI.

    Thank you for your time,
    Scott