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500MHz DDR parallel LVDS bus input timing measurement

Hui
Prodigy 50 points

Hi,

I am doing timing analysis of DAC parallel LVDS bus. I am not clear on the timing measurement between data and strobe.

the timing can be measure in two methods

1, from strobe zero-crossing point to data invalid(measured to +/-200mV)

2, from strobe +/-200mV threshold to data invalid.

in another word, the question is whether the timing penalty of strobe edge should be taken into account or not? 

which method is correct?

Any help is appreciate.

Best regards

Hui

 

 

  • 0
    TI__Genius 17340 points
    Hi Hui,

    Typically we'll measure from the strobe zero-crossing point because that is the best estimate of where data is captured (due to receiver gain). However, for design verification you should add some additional timing margin to account for uncertainty. The +/- 200 mV times are conservative for strobe margin, so the timing of +/-100 mV or +/-50mV are likely better margins to use.

    Regards,
    Matt Guibord
  • 0 in reply to Matt Guibord
    Prodigy 50 points

    Hi Matt,

    Thanks for your quick answer.

    In this case, the added timing margin is dependent on slew rate. However, 50mV still could be conservative if the edge is slow. Can I measure at zero-crossing point and add a few pico seconds (+/-10ps 20ps?) as the additional timing margin instead of measuring at 50mV threshold?

     

    Best regards

    Hui

  • 0 in reply to Hui
    TI__Genius 17340 points

    Hi Hui,

    Yes, I think that approach is probably okay.

    Regards,
    Matt Guibord