ADC parallel LVDS output timing

Hi,

The min setup and hold numbers are how much time we guarantee the signal to be valid before and after the clock edge.  The minimum numbers are the guaranteed values over the full range of supply voltage and full range of ambient temperature that the device is specified to operate over.  So, if a device is specified for an industrial temp range of -40C to 85C and a certain voltage rail is specified to operate over a range of 1.7V to 1.9V with nominal at 1.8V, then we gurantee the setup and hold times will be at least the datasheet mins over any combination of temperatures or supply voltages that are within valid range.   The typical timing numbers are the avarage of what you would see the numbers be at room temperature and at nominal supply voltage.    Min numbers should be used for timing closure.   If you cannot close timing with the datasheet minimums that you see, then your choices would be to move to a faster speed grade FPGA (if you are using an FPGA) or change the way you are latching in the data.  (for example, in an FPGA you might find the option of using a DDR input cell provided by the FPGA vendor that might have tighter timing restrictions than say a input deserializer cell from the vendor's same library so one architecture might be faster than another.)

The guaranteed data setup and hold numbers will include any skew that might be present from one LVDS pair to another, plus any jitter, plus any temperature or voltage dependent changes in skew, but the characteization data does not break out the individual components of the timing so I do not have data on just the jitter component of the timing.

Regards,

Richard P.

Hi Richard,

Your answer is very helpful.

thanks very much!

Best regards

Hui