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ADS8556 serial interface

Keiichi Kajino
Expert 2365 points
Other Parts Discussed in Thread: ADS8556

Hi, folks

I have a three questions as below.

1. Number of SCLKs

If we are using CONV_A and CONV_B and NOT use CONV_C, also only SDO_A uses to out,

Is the serial clock need 96 clock to be flushed all data? or only need 64 clocks?

 

2. SCLK polarity @(negedge nFS)

When nFS is asserted (means 1 to 0), Is the SCLK should be high or do not care?

3. SCLK and nFS timing

Is the nFS should be negated (means 0 to 1) at exact same timing of posedge SCLK? 

Is it OK to apply SCLK first and then negate nFS?

  • 0
    TI__Guru**** 180771 points
    Hi Keiichi,
    If you are only using the CHA and CHB pairs, you only need to clock out the 64 bits of data from those channels. If you are implementing and 'SPI' type interface, SCLK should dwell high with SDI/SDO data being valid on the falling SCLK edge, changing on rising.
  • 0 in reply to Tom Hendrick
    Expert 2365 points

    Tom,

    Thanks for your reply.

    Yesterday I talk with customer and got a question again.

    Our customer tried as follows, but in case of 1st SCLK start from L when nFS assert, the data seems out with bit shifted.

    Does the he ADS8556 need to start SCLK=H when nFS assert? (It means that need SCLk negedge after  nFS assert?)

    Also when using only A/B, if we applied more than 64bits, the undefined CONV_C will be shifted out? 

  • 0 in reply to Keiichi Kajino
    TI__Guru**** 180771 points

    Hi Keiichi,

    Yes, SCLK on the ADS8556 is expected to be high while nFS is asserted low.  If only CONVST A/B are applied, there will not be a conversion of the CH_Cx channels.  If you continue past 64 SCLK cycles in this case, you would read the old conversion data that is still in the CH_Cx buffer.