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ADS7863A SPI interface

Aaron Spaete
Expert 4527 points

Team,

My customer has a simple question on the operation of the SPI interface on the  AD7863A analog to digital converter.

 How does the device respond if the Chip Select pin is returned high before the end of a transaction: 

a) Does the device recovers without latchup? 

b) Is the communication bus transfer aborted?  Is this immediate?

c) How long before a new SPI bus transaction can be started? 

d) If CS_F goes high, is there a minimum time that it must remain high prior to the next communication?

 Note:  The microcontroller communicating with the  AD7863A is the TMS570.

 Regards,

Aaron

 

  • 0
    TI__Guru**** 180941 points

    Hi Aaron,

    The CS/FS pin gates the SDI/O.  When it is high, no SDI is recognized and SDO is deactivated.  If CS/FS is returned high before the end of a transaction, there won't be any latchup, but there could be some corruption of the configuration registers.  

    The configuration details are decoded on the fly so depending on when the chip select went high, some of the details may be lost in the transaction.  There is no "buffer then load" on the input data.  Output data is buffered so assuming there is no re-application of the CONVST input, the same conversion result could be read multiple times as long as CONVST and RD are controlled separately. Communications can restart after the t12 and t4 minimum delay times are met. There is no minimum high time for CS/FS, it can be tied low if desired.